178 lines
6.9 KiB
Plaintext
178 lines
6.9 KiB
Plaintext
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Device tree bindings for MVEBU Device Bus controllers
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The Device Bus controller available in some Marvell's SoC allows to control
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different types of standard memory and I/O devices such as NOR, NAND, and FPGA.
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The actual devices are instantiated from the child nodes of a Device Bus node.
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Required properties:
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- compatible: Armada 370/XP SoC are supported using the
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"marvell,mvebu-devbus" compatible string.
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Orion5x SoC are supported using the
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"marvell,orion-devbus" compatible string.
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- reg: A resource specifier for the register space.
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This is the base address of a chip select within
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the controller's register space.
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(see the example below)
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- #address-cells: Must be set to 1
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- #size-cells: Must be set to 1
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- ranges: Must be set up to reflect the memory layout with four
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integer values for each chip-select line in use:
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0 <physical address of mapping> <size>
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Optional properties:
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- devbus,keep-config This property can optionally be used to keep
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using the timing parameters set by the
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bootloader. It makes all the timing properties
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described below unused.
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Timing properties for child nodes:
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Read parameters:
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- devbus,turn-off-ps: Defines the time during which the controller does not
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drive the AD bus after the completion of a device read.
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This prevents contentions on the Device Bus after a read
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cycle from a slow device.
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Mandatory, except if devbus,keep-config is used.
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- devbus,bus-width: Defines the bus width, in bits (e.g. <16>).
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Mandatory, except if devbus,keep-config is used.
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- devbus,badr-skew-ps: Defines the time delay from from A[2:0] toggle,
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to read data sample. This parameter is useful for
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synchronous pipelined devices, where the address
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precedes the read data by one or two cycles.
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Mandatory, except if devbus,keep-config is used.
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- devbus,acc-first-ps: Defines the time delay from the negation of
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ALE[0] to the cycle that the first read data is sampled
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by the controller.
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Mandatory, except if devbus,keep-config is used.
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- devbus,acc-next-ps: Defines the time delay between the cycle that
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samples data N and the cycle that samples data N+1
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(in burst accesses).
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Mandatory, except if devbus,keep-config is used.
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- devbus,rd-setup-ps: Defines the time delay between DEV_CSn assertion to
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DEV_OEn assertion. If set to 0 (default),
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DEV_OEn and DEV_CSn are asserted at the same cycle.
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This parameter has no affect on <acc-first-ps> parameter
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(no affect on first data sample). Set <rd-setup-ps>
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to a value smaller than <acc-first-ps>.
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Mandatory for "marvell,mvebu-devbus" compatible string,
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except if devbus,keep-config is used.
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- devbus,rd-hold-ps: Defines the time between the last data sample to the
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de-assertion of DEV_CSn. If set to 0 (default),
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DEV_OEn and DEV_CSn are de-asserted at the same cycle
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(the cycle of the last data sample).
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This parameter has no affect on DEV_OEn de-assertion.
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DEV_OEn is always de-asserted the next cycle after
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last data sampled. Also this parameter has no
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affect on <turn-off-ps> parameter.
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Set <rd-hold-ps> to a value smaller than <turn-off-ps>.
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Mandatory for "marvell,mvebu-devbus" compatible string,
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except if devbus,keep-config is used.
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Write parameters:
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- devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
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to the DEV_WEn assertion.
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Mandatory.
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- devbus,wr-low-ps: Defines the time during which DEV_WEn is active.
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A[2:0] and Data are kept valid as long as DEV_WEn
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is active. This parameter defines the setup time of
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address and data to DEV_WEn rise.
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Mandatory.
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- devbus,wr-high-ps: Defines the time during which DEV_WEn is kept
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inactive (high) between data beats of a burst write.
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DEV_A[2:0] and Data are kept valid (do not toggle) for
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<wr-high-ps> - <tick> ps.
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This parameter defines the hold time of address and
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data after DEV_WEn rise.
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Mandatory.
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- devbus,sync-enable: Synchronous device enable.
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1: True
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0: False
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Mandatory for "marvell,mvebu-devbus" compatible string,
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except if devbus,keep-config is used.
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An example for an Armada XP GP board, with a 16 MiB NOR device as child
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is showed below. Note that the Device Bus driver is in charge of allocating
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the mbus address decoding window for each of its child devices.
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The window is created using the chip select specified in the child
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device node together with the base address and size specified in the ranges
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property. For instance, in the example below the allocated decoding window
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will start at base address 0xf0000000, with a size 0x1000000 (16 MiB)
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for chip select 0 (a.k.a DEV_BOOTCS).
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This address window handling is done in this mvebu-devbus only as a temporary
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solution. It will be removed when the support for mbus device tree binding is
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added.
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The reg property implicitly specifies the chip select as this:
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0x10400: DEV_BOOTCS
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0x10408: DEV_CS0
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0x10410: DEV_CS1
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0x10418: DEV_CS2
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0x10420: DEV_CS3
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Example:
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devbus-bootcs@d0010400 {
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ranges = <0 0xf0000000 0x1000000>; /* @addr 0xf0000000, size 0x1000000 */
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#address-cells = <1>;
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#size-cells = <1>;
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/* Device Bus parameters are required */
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/* Read parameters */
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devbus,bus-width = <8>;
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devbus,turn-off-ps = <60000>;
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devbus,badr-skew-ps = <0>;
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devbus,acc-first-ps = <124000>;
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devbus,acc-next-ps = <248000>;
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devbus,rd-setup-ps = <0>;
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devbus,rd-hold-ps = <0>;
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/* Write parameters */
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devbus,sync-enable = <0>;
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devbus,wr-high-ps = <60000>;
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devbus,wr-low-ps = <60000>;
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devbus,ale-wr-ps = <60000>;
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flash@0 {
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compatible = "cfi-flash";
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/* 16 MiB */
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reg = <0 0x1000000>;
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bank-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* We split the 16 MiB in two partitions,
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* just as an example.
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*/
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partition@0 {
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label = "First";
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reg = <0 0x800000>;
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};
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partition@800000 {
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label = "Second";
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reg = <0x800000 0x800000>;
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};
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};
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};
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