kernel_samsung_a34x-permissive/Documentation/devicetree/bindings/net/mediatek-dwmac.txt

MediaTek DWMAC glue layer controller

This file documents platform glue layer for stmmac.
Please see stmmac.txt for the other unchanged properties.

The device node has following properties.

Required properties:
- compatible:  Should be "mediatek,mt2712-gmac" for MT2712 SoC
- reg:  Address and length of the register set for the device
- interrupts:  Should contain the MAC interrupts
- interrupt-names: Should contain a list of interrupt names corresponding to
	the interrupts in the interrupts property, if available.
	Should be "macirq" for the main MAC IRQ
- clocks: Must contain a phandle for each entry in clock-names.
- clock-names: The name of the clock listed in the clocks property. These are
	"axi", "apb", "mac_main", "ptp_ref" for MT2712 SoC
- mac-address: See ethernet.txt in the same directory
- phy-mode: See ethernet.txt in the same directory
- mediatek,pericfg: A phandle to the syscon node that control ethernet
	interface and timing delay.

Optional properties:
- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0.
	It should be defined for rgmii/rgmii-rxid/mii interface.
- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0.
	It should be defined for rgmii/rgmii-txid/mii/rmii interface.
Both delay properties need to be a multiple of 170 for fine-tune rgmii,
range 0~31*170.
Both delay properties need to be a multiple of 550 for coarse-tune rgmii,
range 0~31*550.
Both delay properties need to be a multiple of 550 for mii/rmii,
range 0~31*550.

- mediatek,fine-tune: boolean property, if present indicates that fine delay
	is selected for rgmii interface.
	If present, tx-delay-ps/rx-delay-ps is 170+/-50ps per stage.
	Else tx-delay-ps/rx-delay-ps of coarse delay macro is 0.55+/-0.2ns per stage.
	This property do not apply to non-rgmii PHYs.
	Only coarse-tune delay is supported for mii/rmii PHYs.
- mediatek,rmii-rxc: boolean property, if present indicates that the rmii
	reference clock, which is from external PHYs, is connected to RXC pin
	on MT2712 SoC.
	Otherwise, is connected to TXC pin.
- mediatek,txc-inverse: boolean property, if present indicates that
	1. tx clock will be inversed in mii/rgmii case,
	2. tx clock inside MAC will be inversed relative to reference clock
	   which is from external PHYs in rmii case, and it rarely happen.
- mediatek,rxc-inverse: boolean property, if present indicates that
	1. rx clock will be inversed in mii/rgmii case.
	2. reference clock will be inversed when arrived at MAC in rmii case.
- assigned-clocks: mac_main and ptp_ref clocks
- assigned-clock-parents: parent clocks of the assigned clocks

Example:
	eth: ethernet@1101c000 {
		compatible = "mediatek,mt2712-gmac";
		reg = <0 0x1101c000 0 0x1300>;
		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
		interrupt-names = "macirq";
		phy-mode ="rgmii";
		mac-address = [00 55 7b b5 7d f7];
		clock-names = "axi",
			      "apb",
			      "mac_main",
			      "ptp_ref",
			      "ptp_top";
		clocks = <&pericfg CLK_PERI_GMAC>,
			 <&pericfg CLK_PERI_GMAC_PCLK>,
			 <&topckgen CLK_TOP_ETHER_125M_SEL>,
			 <&topckgen CLK_TOP_ETHER_50M_SEL>;
		assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
				  <&topckgen CLK_TOP_ETHER_50M_SEL>;
		assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
					 <&topckgen CLK_TOP_APLL1_D3>;
		mediatek,pericfg = <&pericfg>;
		mediatek,tx-delay-ps = <1530>;
		mediatek,rx-delay-ps = <1530>;
		mediatek,fine-tune;
		mediatek,rmii-rxc;
		mediatek,txc-inverse;
		mediatek,rxc-inverse;
		snps,txpbl = <32>;
		snps,rxpbl = <32>;
		snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
		snps,reset-active-low;
	};