52 lines
1.6 KiB
Plaintext
52 lines
1.6 KiB
Plaintext
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Driver i2c-mlxcpld
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Author: Michael Shych <michaelsh@mellanox.com>
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This is the Mellanox I2C controller logic, implemented in Lattice CPLD
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device.
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Device supports:
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- Master mode.
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- One physical bus.
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- Polling mode.
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This controller is equipped within the next Mellanox systems:
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"msx6710", "msx6720", "msb7700", "msn2700", "msx1410", "msn2410", "msb7800",
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"msn2740", "msn2100".
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The next transaction types are supported:
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- Receive Byte/Block.
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- Send Byte/Block.
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- Read Byte/Block.
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- Write Byte/Block.
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Registers:
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CPBLTY 0x0 - capability reg.
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Bits [6:5] - transaction length. b01 - 72B is supported,
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36B in other case.
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Bit 7 - SMBus block read support.
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CTRL 0x1 - control reg.
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Resets all the registers.
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HALF_CYC 0x4 - cycle reg.
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Configure the width of I2C SCL half clock cycle (in 4 LPC_CLK
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units).
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I2C_HOLD 0x5 - hold reg.
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OE (output enable) is delayed by value set to this register
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(in LPC_CLK units)
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CMD 0x6 - command reg.
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Bit 0, 0 = write, 1 = read.
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Bits [7:1] - the 7bit Address of the I2C device.
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It should be written last as it triggers an I2C transaction.
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NUM_DATA 0x7 - data size reg.
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Number of data bytes to write in read transaction
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NUM_ADDR 0x8 - address reg.
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Number of address bytes to write in read transaction.
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STATUS 0x9 - status reg.
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Bit 0 - transaction is completed.
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Bit 4 - ACK/NACK.
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DATAx 0xa - 0x54 - 68 bytes data buffer regs.
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For write transaction address is specified in four first bytes
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(DATA1 - DATA4), data starting from DATA4.
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For read transactions address is sent in a separate transaction and
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specified in the four first bytes (DATA0 - DATA3). Data is read
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starting from DATA0.
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