318 lines
7.6 KiB
C
318 lines
7.6 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* arch/arm/mach-ixp4xx/ixdp425-setup.c
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*
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* IXDP425/IXCDP1100 board-setup
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*
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* Copyright (C) 2003-2005 MontaVista Software, Inc.
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*
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* Author: Deepak Saxena <dsaxena@plexity.net>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/device.h>
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#include <linux/serial.h>
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#include <linux/tty.h>
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#include <linux/serial_8250.h>
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#include <linux/gpio/machine.h>
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#include <linux/io.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/delay.h>
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#include <linux/gpio.h>
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#include <asm/types.h>
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#include <asm/setup.h>
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#include <asm/memory.h>
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#include <mach/hardware.h>
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#include <asm/mach-types.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#define IXDP425_SDA_PIN 7
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#define IXDP425_SCL_PIN 6
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/* NAND Flash pins */
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#define IXDP425_NAND_NCE_PIN 12
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#define IXDP425_NAND_CMD_BYTE 0x01
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#define IXDP425_NAND_ADDR_BYTE 0x02
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static struct flash_platform_data ixdp425_flash_data = {
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.map_name = "cfi_probe",
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.width = 2,
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};
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static struct resource ixdp425_flash_resource = {
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device ixdp425_flash = {
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.name = "IXP4XX-Flash",
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.id = 0,
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.dev = {
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.platform_data = &ixdp425_flash_data,
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},
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.num_resources = 1,
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.resource = &ixdp425_flash_resource,
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};
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#if defined(CONFIG_MTD_NAND_PLATFORM) || \
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defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
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static struct mtd_partition ixdp425_partitions[] = {
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{
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.name = "ixp400 NAND FS 0",
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.offset = 0,
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.size = SZ_8M
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}, {
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.name = "ixp400 NAND FS 1",
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.offset = MTDPART_OFS_APPEND,
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.size = MTDPART_SIZ_FULL
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},
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};
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static void
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ixdp425_flash_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd_to_nand(mtd);
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int offset = (int)nand_get_controller_data(this);
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_NCE) {
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gpio_set_value(IXDP425_NAND_NCE_PIN, 0);
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udelay(5);
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} else
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gpio_set_value(IXDP425_NAND_NCE_PIN, 1);
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offset = (ctrl & NAND_CLE) ? IXDP425_NAND_CMD_BYTE : 0;
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offset |= (ctrl & NAND_ALE) ? IXDP425_NAND_ADDR_BYTE : 0;
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nand_set_controller_data(this, (void *)offset);
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W + offset);
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}
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static struct platform_nand_data ixdp425_flash_nand_data = {
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.chip = {
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.nr_chips = 1,
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.chip_delay = 30,
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.partitions = ixdp425_partitions,
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.nr_partitions = ARRAY_SIZE(ixdp425_partitions),
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},
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.ctrl = {
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.cmd_ctrl = ixdp425_flash_nand_cmd_ctrl
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}
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};
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static struct resource ixdp425_flash_nand_resource = {
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device ixdp425_flash_nand = {
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.name = "gen_nand",
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.id = -1,
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.dev = {
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.platform_data = &ixdp425_flash_nand_data,
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},
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.num_resources = 1,
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.resource = &ixdp425_flash_nand_resource,
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};
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#endif /* CONFIG_MTD_NAND_PLATFORM */
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static struct gpiod_lookup_table ixdp425_i2c_gpiod_table = {
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.dev_id = "i2c-gpio.0",
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.table = {
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GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SDA_PIN,
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NULL, 0, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
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GPIO_LOOKUP_IDX("IXP4XX_GPIO_CHIP", IXDP425_SCL_PIN,
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NULL, 1, GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN),
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},
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};
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static struct platform_device ixdp425_i2c_gpio = {
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.name = "i2c-gpio",
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.id = 0,
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.dev = {
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.platform_data = NULL,
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},
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};
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static struct resource ixdp425_uart_resources[] = {
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{
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.start = IXP4XX_UART1_BASE_PHYS,
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.end = IXP4XX_UART1_BASE_PHYS + 0x0fff,
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.flags = IORESOURCE_MEM
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},
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{
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.start = IXP4XX_UART2_BASE_PHYS,
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.end = IXP4XX_UART2_BASE_PHYS + 0x0fff,
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.flags = IORESOURCE_MEM
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}
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};
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static struct plat_serial8250_port ixdp425_uart_data[] = {
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{
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.mapbase = IXP4XX_UART1_BASE_PHYS,
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.membase = (char *)IXP4XX_UART1_BASE_VIRT + REG_OFFSET,
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.irq = IRQ_IXP4XX_UART1,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = IXP4XX_UART_XTAL,
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},
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{
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.mapbase = IXP4XX_UART2_BASE_PHYS,
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.membase = (char *)IXP4XX_UART2_BASE_VIRT + REG_OFFSET,
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.irq = IRQ_IXP4XX_UART2,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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.iotype = UPIO_MEM,
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.regshift = 2,
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.uartclk = IXP4XX_UART_XTAL,
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},
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{ },
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};
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static struct platform_device ixdp425_uart = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev.platform_data = ixdp425_uart_data,
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.num_resources = 2,
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.resource = ixdp425_uart_resources
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};
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/* Built-in 10/100 Ethernet MAC interfaces */
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static struct eth_plat_info ixdp425_plat_eth[] = {
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{
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.phy = 0,
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.rxq = 3,
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.txreadyq = 20,
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}, {
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.phy = 1,
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.rxq = 4,
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.txreadyq = 21,
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}
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};
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static struct platform_device ixdp425_eth[] = {
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{
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.name = "ixp4xx_eth",
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.id = IXP4XX_ETH_NPEB,
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.dev.platform_data = ixdp425_plat_eth,
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}, {
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.name = "ixp4xx_eth",
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.id = IXP4XX_ETH_NPEC,
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.dev.platform_data = ixdp425_plat_eth + 1,
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}
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};
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static struct platform_device *ixdp425_devices[] __initdata = {
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&ixdp425_i2c_gpio,
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&ixdp425_flash,
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#if defined(CONFIG_MTD_NAND_PLATFORM) || \
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defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
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&ixdp425_flash_nand,
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#endif
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&ixdp425_uart,
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&ixdp425_eth[0],
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&ixdp425_eth[1],
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};
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static void __init ixdp425_init(void)
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{
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ixp4xx_sys_init();
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ixdp425_flash_resource.start = IXP4XX_EXP_BUS_BASE(0);
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ixdp425_flash_resource.end =
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IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
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#if defined(CONFIG_MTD_NAND_PLATFORM) || \
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defined(CONFIG_MTD_NAND_PLATFORM_MODULE)
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ixdp425_flash_nand_resource.start = IXP4XX_EXP_BUS_BASE(3),
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ixdp425_flash_nand_resource.end = IXP4XX_EXP_BUS_BASE(3) + 0x10 - 1;
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gpio_request(IXDP425_NAND_NCE_PIN, "NAND NCE pin");
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gpio_direction_output(IXDP425_NAND_NCE_PIN, 0);
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/* Configure expansion bus for NAND Flash */
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*IXP4XX_EXP_CS3 = IXP4XX_EXP_BUS_CS_EN |
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IXP4XX_EXP_BUS_STROBE_T(1) | /* extend by 1 clock */
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IXP4XX_EXP_BUS_CYCLES(0) | /* Intel cycles */
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IXP4XX_EXP_BUS_SIZE(0) | /* 512bytes addr space*/
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IXP4XX_EXP_BUS_WR_EN |
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IXP4XX_EXP_BUS_BYTE_EN; /* 8 bit data bus */
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#endif
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if (cpu_is_ixp43x()) {
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ixdp425_uart.num_resources = 1;
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ixdp425_uart_data[1].flags = 0;
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}
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gpiod_add_lookup_table(&ixdp425_i2c_gpiod_table);
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platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
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}
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#ifdef CONFIG_ARCH_IXDP425
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MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
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/* Maintainer: MontaVista Software, Inc. */
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.map_io = ixp4xx_map_io,
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.init_early = ixp4xx_init_early,
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.init_irq = ixp4xx_init_irq,
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.init_time = ixp4xx_timer_init,
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.atag_offset = 0x100,
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.init_machine = ixdp425_init,
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#if defined(CONFIG_PCI)
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.dma_zone_size = SZ_64M,
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#endif
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.restart = ixp4xx_restart,
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MACHINE_END
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#endif
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#ifdef CONFIG_MACH_IXDP465
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MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
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/* Maintainer: MontaVista Software, Inc. */
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.map_io = ixp4xx_map_io,
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.init_early = ixp4xx_init_early,
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.init_irq = ixp4xx_init_irq,
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.init_time = ixp4xx_timer_init,
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.atag_offset = 0x100,
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.init_machine = ixdp425_init,
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#if defined(CONFIG_PCI)
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.dma_zone_size = SZ_64M,
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#endif
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MACHINE_END
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#endif
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#ifdef CONFIG_ARCH_PRPMC1100
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MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
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/* Maintainer: MontaVista Software, Inc. */
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.map_io = ixp4xx_map_io,
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.init_early = ixp4xx_init_early,
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.init_irq = ixp4xx_init_irq,
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.init_time = ixp4xx_timer_init,
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.atag_offset = 0x100,
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.init_machine = ixdp425_init,
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#if defined(CONFIG_PCI)
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.dma_zone_size = SZ_64M,
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#endif
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MACHINE_END
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#endif
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#ifdef CONFIG_MACH_KIXRP435
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MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
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/* Maintainer: MontaVista Software, Inc. */
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.map_io = ixp4xx_map_io,
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.init_early = ixp4xx_init_early,
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.init_irq = ixp4xx_init_irq,
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.init_time = ixp4xx_timer_init,
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.atag_offset = 0x100,
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.init_machine = ixdp425_init,
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#if defined(CONFIG_PCI)
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.dma_zone_size = SZ_64M,
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#endif
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MACHINE_END
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#endif
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