436 lines
12 KiB
Plaintext
436 lines
12 KiB
Plaintext
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/*
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* Device Tree Source for AMCC Kilauea (405EX)
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*
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* Copyright 2007-2009 DENX Software Engineering, Stefan Roese <sr@denx.de>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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/dts-v1/;
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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model = "amcc,kilauea";
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compatible = "amcc,kilauea";
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dcr-parent = <&{/cpus/cpu@0}>;
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aliases {
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ethernet0 = &EMAC0;
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ethernet1 = &EMAC1;
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serial0 = &UART0;
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serial1 = &UART1;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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model = "PowerPC,405EX";
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reg = <0x00000000>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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timebase-frequency = <0>; /* Filled in by U-Boot */
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i-cache-line-size = <32>;
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d-cache-line-size = <32>;
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i-cache-size = <16384>; /* 16 kB */
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d-cache-size = <16384>; /* 16 kB */
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dcr-controller;
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dcr-access-method = "native";
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};
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};
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memory {
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device_type = "memory";
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reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
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};
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UIC0: interrupt-controller {
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compatible = "ibm,uic-405ex", "ibm,uic";
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interrupt-controller;
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cell-index = <0>;
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dcr-reg = <0x0c0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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};
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UIC1: interrupt-controller1 {
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compatible = "ibm,uic-405ex","ibm,uic";
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interrupt-controller;
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cell-index = <1>;
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dcr-reg = <0x0d0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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UIC2: interrupt-controller2 {
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compatible = "ibm,uic-405ex","ibm,uic";
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interrupt-controller;
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cell-index = <2>;
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dcr-reg = <0x0e0 0x009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <0x1c 0x4 0x1d 0x4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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CPM0: cpm {
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compatible = "ibm,cpm";
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dcr-access-method = "native";
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dcr-reg = <0x0b0 0x003>;
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unused-units = <0x00000000>;
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idle-doze = <0x02000000>;
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standby = <0xe3e74800>;
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};
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plb {
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compatible = "ibm,plb-405ex", "ibm,plb4";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clock-frequency = <0>; /* Filled in by U-Boot */
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SDRAM0: memory-controller {
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compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
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dcr-reg = <0x010 0x002>;
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interrupt-parent = <&UIC2>;
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interrupts = <0x5 0x4 /* ECC DED Error */
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0x6 0x4>; /* ECC SEC Error */
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};
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CRYPTO: crypto@ef700000 {
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compatible = "amcc,ppc405ex-crypto", "amcc,ppc4xx-crypto";
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reg = <0xef700000 0x80400>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x17 0x2>;
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};
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MAL0: mcmal {
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compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
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dcr-reg = <0x180 0x062>;
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num-tx-chans = <2>;
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num-rx-chans = <2>;
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interrupt-parent = <&MAL0>;
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interrupts = <0x0 0x1 0x2 0x3 0x4>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
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/*RXEOB*/ 0x1 &UIC0 0xb 0x4
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/*SERR*/ 0x2 &UIC1 0x0 0x4
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/*TXDE*/ 0x3 &UIC1 0x1 0x4
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/*RXDE*/ 0x4 &UIC1 0x2 0x4>;
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interrupt-map-mask = <0xffffffff>;
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};
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POB0: opb {
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compatible = "ibm,opb-405ex", "ibm,opb";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x80000000 0x80000000 0x10000000
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0xef600000 0xef600000 0x00a00000
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0xf0000000 0xf0000000 0x10000000>;
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dcr-reg = <0x0a0 0x005>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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EBC0: ebc {
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compatible = "ibm,ebc-405ex", "ibm,ebc";
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dcr-reg = <0x012 0x002>;
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#address-cells = <2>;
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#size-cells = <1>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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/* ranges property is supplied by U-Boot */
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interrupts = <0x5 0x1>;
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interrupt-parent = <&UIC1>;
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nor_flash@0,0 {
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compatible = "amd,s29gl512n", "cfi-flash";
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bank-width = <2>;
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reg = <0x00000000 0x00000000 0x04000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x00000000 0x001e0000>;
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};
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partition@1e0000 {
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label = "dtb";
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reg = <0x001e0000 0x00020000>;
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};
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partition@200000 {
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label = "root";
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reg = <0x00200000 0x00200000>;
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};
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partition@400000 {
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label = "user";
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reg = <0x00400000 0x03b60000>;
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};
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partition@3f60000 {
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label = "env";
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reg = <0x03f60000 0x00040000>;
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};
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partition@3fa0000 {
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label = "u-boot";
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reg = <0x03fa0000 0x00060000>;
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};
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};
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ndfc@1,0 {
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compatible = "ibm,ndfc";
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reg = <0x00000001 0x00000000 0x00002000>;
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ccr = <0x00001000>;
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bank-settings = <0x80002222>;
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#address-cells = <1>;
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#size-cells = <1>;
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nand {
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x00000000 0x00100000>;
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};
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partition@100000 {
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label = "user";
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reg = <0x00000000 0x03f00000>;
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};
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};
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};
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};
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UART0: serial@ef600200 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0xef600200 0x00000008>;
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virtual-reg = <0xef600200>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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current-speed = <0>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x1a 0x4>;
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};
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UART1: serial@ef600300 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <0xef600300 0x00000008>;
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virtual-reg = <0xef600300>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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current-speed = <0>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x1 0x4>;
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};
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IIC0: i2c@ef600400 {
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compatible = "ibm,iic-405ex", "ibm,iic";
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reg = <0xef600400 0x00000014>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x2 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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rtc@68 {
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compatible = "dallas,ds1338";
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reg = <0x68>;
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};
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dtt@48 {
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compatible = "dallas,ds1775";
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reg = <0x48>;
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};
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};
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IIC1: i2c@ef600500 {
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compatible = "ibm,iic-405ex", "ibm,iic";
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reg = <0xef600500 0x00000014>;
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interrupt-parent = <&UIC0>;
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interrupts = <0x7 0x4>;
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};
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RGMII0: emac-rgmii@ef600b00 {
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compatible = "ibm,rgmii-405ex", "ibm,rgmii";
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reg = <0xef600b00 0x00000104>;
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has-mdio;
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};
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EMAC0: ethernet@ef600900 {
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linux,network-index = <0x0>;
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device_type = "network";
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compatible = "ibm,emac-405ex", "ibm,emac4sync";
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interrupt-parent = <&EMAC0>;
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interrupts = <0x0 0x1>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
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/*Wake*/ 0x1 &UIC1 0x1d 0x4>;
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reg = <0xef600900 0x000000c4>;
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local-mac-address = [000000000000]; /* Filled in by U-Boot */
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mal-device = <&MAL0>;
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mal-tx-channel = <0>;
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mal-rx-channel = <0>;
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cell-index = <0>;
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max-frame-size = <9000>;
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rx-fifo-size = <4096>;
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tx-fifo-size = <2048>;
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rx-fifo-size-gige = <16384>;
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tx-fifo-size-gige = <16384>;
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phy-mode = "rgmii";
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phy-map = <0x00000000>;
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rgmii-device = <&RGMII0>;
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rgmii-channel = <0>;
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has-inverted-stacr-oc;
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has-new-stacr-staopc;
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};
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EMAC1: ethernet@ef600a00 {
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linux,network-index = <0x1>;
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device_type = "network";
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compatible = "ibm,emac-405ex", "ibm,emac4sync";
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interrupt-parent = <&EMAC1>;
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interrupts = <0x0 0x1>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
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/*Wake*/ 0x1 &UIC1 0x1f 0x4>;
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reg = <0xef600a00 0x000000c4>;
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local-mac-address = [000000000000]; /* Filled in by U-Boot */
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mal-device = <&MAL0>;
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mal-tx-channel = <1>;
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mal-rx-channel = <1>;
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cell-index = <1>;
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max-frame-size = <9000>;
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rx-fifo-size = <4096>;
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tx-fifo-size = <2048>;
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rx-fifo-size-gige = <16384>;
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tx-fifo-size-gige = <16384>;
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phy-mode = "rgmii";
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phy-map = <0x00000000>;
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rgmii-device = <&RGMII0>;
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rgmii-channel = <1>;
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has-inverted-stacr-oc;
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has-new-stacr-staopc;
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};
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};
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PCIE0: pciex@a0000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
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primary;
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port = <0x0>; /* port number */
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reg = <0xa0000000 0x20000000 /* Config space access */
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0xef000000 0x00001000>; /* Registers */
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dcr-reg = <0x040 0x020>;
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sdr-base = <0x400>;
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed
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*/
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ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
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0x01000000 0x00000000 0x00000000 0xe0000000 0x00000000 0x00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
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/* This drives busses 0x00 to 0x3f */
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bus-range = <0x0 0x3f>;
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/* Legacy interrupts (note the weird polarity, the bridge seems
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* to invert PCIe legacy interrupts).
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* We are de-swizzling here because the numbers are actually for
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* port of the root complex virtual P2P bridge. But I want
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* to avoid putting a node for it in the tree, so the numbers
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* below are basically de-swizzled numbers.
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* The real slot is on idsel 0, so the swizzling is 1:1
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*/
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <
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0x0 0x0 0x0 0x1 &UIC2 0x0 0x4 /* swizzled int A */
|
||
|
|
0x0 0x0 0x0 0x2 &UIC2 0x1 0x4 /* swizzled int B */
|
||
|
|
0x0 0x0 0x0 0x3 &UIC2 0x2 0x4 /* swizzled int C */
|
||
|
|
0x0 0x0 0x0 0x4 &UIC2 0x3 0x4 /* swizzled int D */>;
|
||
|
|
};
|
||
|
|
|
||
|
|
PCIE1: pciex@c0000000 {
|
||
|
|
device_type = "pci";
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
#size-cells = <2>;
|
||
|
|
#address-cells = <3>;
|
||
|
|
compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
|
||
|
|
primary;
|
||
|
|
port = <0x1>; /* port number */
|
||
|
|
reg = <0xc0000000 0x20000000 /* Config space access */
|
||
|
|
0xef001000 0x00001000>; /* Registers */
|
||
|
|
dcr-reg = <0x060 0x020>;
|
||
|
|
sdr-base = <0x440>;
|
||
|
|
|
||
|
|
/* Outbound ranges, one memory and one IO,
|
||
|
|
* later cannot be changed
|
||
|
|
*/
|
||
|
|
ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
|
||
|
|
0x01000000 0x00000000 0x00000000 0xe0010000 0x00000000 0x00010000>;
|
||
|
|
|
||
|
|
/* Inbound 2GB range starting at 0 */
|
||
|
|
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
|
||
|
|
|
||
|
|
/* This drives busses 0x40 to 0x7f */
|
||
|
|
bus-range = <0x40 0x7f>;
|
||
|
|
|
||
|
|
/* Legacy interrupts (note the weird polarity, the bridge seems
|
||
|
|
* to invert PCIe legacy interrupts).
|
||
|
|
* We are de-swizzling here because the numbers are actually for
|
||
|
|
* port of the root complex virtual P2P bridge. But I want
|
||
|
|
* to avoid putting a node for it in the tree, so the numbers
|
||
|
|
* below are basically de-swizzled numbers.
|
||
|
|
* The real slot is on idsel 0, so the swizzling is 1:1
|
||
|
|
*/
|
||
|
|
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
|
||
|
|
interrupt-map = <
|
||
|
|
0x0 0x0 0x0 0x1 &UIC2 0xb 0x4 /* swizzled int A */
|
||
|
|
0x0 0x0 0x0 0x2 &UIC2 0xc 0x4 /* swizzled int B */
|
||
|
|
0x0 0x0 0x0 0x3 &UIC2 0xd 0x4 /* swizzled int C */
|
||
|
|
0x0 0x0 0x0 0x4 &UIC2 0xe 0x4 /* swizzled int D */>;
|
||
|
|
};
|
||
|
|
|
||
|
|
MSI: ppc4xx-msi@C10000000 {
|
||
|
|
compatible = "amcc,ppc4xx-msi", "ppc4xx-msi";
|
||
|
|
reg = <0xEF620000 0x100>;
|
||
|
|
sdr-base = <0x4B0>;
|
||
|
|
msi-data = <0x00000000>;
|
||
|
|
msi-mask = <0x44440000>;
|
||
|
|
interrupt-count = <12>;
|
||
|
|
interrupts = <0 1 2 3 4 5 6 7 8 9 0xA 0xB 0xC 0xD>;
|
||
|
|
interrupt-parent = <&UIC2>;
|
||
|
|
#interrupt-cells = <1>;
|
||
|
|
#address-cells = <0>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
interrupt-map = <0 &UIC2 0x10 1
|
||
|
|
1 &UIC2 0x11 1
|
||
|
|
2 &UIC2 0x12 1
|
||
|
|
2 &UIC2 0x13 1
|
||
|
|
2 &UIC2 0x14 1
|
||
|
|
2 &UIC2 0x15 1
|
||
|
|
2 &UIC2 0x16 1
|
||
|
|
2 &UIC2 0x17 1
|
||
|
|
2 &UIC2 0x18 1
|
||
|
|
2 &UIC2 0x19 1
|
||
|
|
2 &UIC2 0x1A 1
|
||
|
|
2 &UIC2 0x1B 1
|
||
|
|
2 &UIC2 0x1C 1
|
||
|
|
3 &UIC2 0x1D 1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|