419 lines
11 KiB
C
419 lines
11 KiB
C
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/*
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* RNG driver for Intel RNGs
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*
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* Copyright 2005 (c) MontaVista Software, Inc.
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*
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* with the majority of the code coming from:
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*
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* Hardware driver for the Intel/AMD/VIA Random Number Generators (RNG)
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* (c) Copyright 2003 Red Hat Inc <jgarzik@redhat.com>
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*
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* derived from
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*
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* Hardware driver for the AMD 768 Random Number Generator (RNG)
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* (c) Copyright 2001 Red Hat Inc
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*
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* derived from
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*
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* Hardware driver for Intel i810 Random Number Generator (RNG)
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* Copyright 2000,2001 Jeff Garzik <jgarzik@pobox.com>
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* Copyright 2000,2001 Philipp Rumpf <prumpf@mandrakesoft.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/hw_random.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/stop_machine.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <asm/io.h>
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#define PFX KBUILD_MODNAME ": "
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/*
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* RNG registers
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*/
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#define INTEL_RNG_HW_STATUS 0
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#define INTEL_RNG_PRESENT 0x40
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#define INTEL_RNG_ENABLED 0x01
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#define INTEL_RNG_STATUS 1
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#define INTEL_RNG_DATA_PRESENT 0x01
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#define INTEL_RNG_DATA 2
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/*
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* Magic address at which Intel PCI bridges locate the RNG
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*/
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#define INTEL_RNG_ADDR 0xFFBC015F
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#define INTEL_RNG_ADDR_LEN 3
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/*
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* LPC bridge PCI config space registers
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*/
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#define FWH_DEC_EN1_REG_OLD 0xe3
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#define FWH_DEC_EN1_REG_NEW 0xd9 /* high byte of 16-bit register */
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#define FWH_F8_EN_MASK 0x80
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#define BIOS_CNTL_REG_OLD 0x4e
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#define BIOS_CNTL_REG_NEW 0xdc
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#define BIOS_CNTL_WRITE_ENABLE_MASK 0x01
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#define BIOS_CNTL_LOCK_ENABLE_MASK 0x02
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/*
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* Magic address at which Intel Firmware Hubs get accessed
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*/
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#define INTEL_FWH_ADDR 0xffff0000
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#define INTEL_FWH_ADDR_LEN 2
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/*
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* Intel Firmware Hub command codes (write to any address inside the device)
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*/
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#define INTEL_FWH_RESET_CMD 0xff /* aka READ_ARRAY */
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#define INTEL_FWH_READ_ID_CMD 0x90
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/*
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* Intel Firmware Hub Read ID command result addresses
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*/
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#define INTEL_FWH_MANUFACTURER_CODE_ADDRESS 0x000000
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#define INTEL_FWH_DEVICE_CODE_ADDRESS 0x000001
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/*
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* Intel Firmware Hub Read ID command result values
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*/
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#define INTEL_FWH_MANUFACTURER_CODE 0x89
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#define INTEL_FWH_DEVICE_CODE_8M 0xac
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#define INTEL_FWH_DEVICE_CODE_4M 0xad
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/*
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* Data for PCI driver interface
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*
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* This data only exists for exporting the supported
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* PCI ids via MODULE_DEVICE_TABLE. We do not actually
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* register a pci_driver, because someone else might one day
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* want to register another driver on the same PCI id.
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*/
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static const struct pci_device_id pci_tbl[] = {
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/* AA
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{ PCI_DEVICE(0x8086, 0x2418) }, */
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{ PCI_DEVICE(0x8086, 0x2410) }, /* AA */
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/* AB
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{ PCI_DEVICE(0x8086, 0x2428) }, */
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{ PCI_DEVICE(0x8086, 0x2420) }, /* AB */
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/* ??
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{ PCI_DEVICE(0x8086, 0x2430) }, */
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/* BAM, CAM, DBM, FBM, GxM
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{ PCI_DEVICE(0x8086, 0x2448) }, */
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{ PCI_DEVICE(0x8086, 0x244c) }, /* BAM */
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{ PCI_DEVICE(0x8086, 0x248c) }, /* CAM */
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{ PCI_DEVICE(0x8086, 0x24cc) }, /* DBM */
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{ PCI_DEVICE(0x8086, 0x2641) }, /* FBM */
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{ PCI_DEVICE(0x8086, 0x27b9) }, /* GxM */
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{ PCI_DEVICE(0x8086, 0x27bd) }, /* GxM DH */
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/* BA, CA, DB, Ex, 6300, Fx, 631x/632x, Gx
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{ PCI_DEVICE(0x8086, 0x244e) }, */
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{ PCI_DEVICE(0x8086, 0x2440) }, /* BA */
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{ PCI_DEVICE(0x8086, 0x2480) }, /* CA */
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{ PCI_DEVICE(0x8086, 0x24c0) }, /* DB */
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{ PCI_DEVICE(0x8086, 0x24d0) }, /* Ex */
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{ PCI_DEVICE(0x8086, 0x25a1) }, /* 6300 */
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{ PCI_DEVICE(0x8086, 0x2640) }, /* Fx */
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{ PCI_DEVICE(0x8086, 0x2670) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x2671) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x2672) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x2673) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x2674) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x2675) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x2676) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x2677) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x2678) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x2679) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x267a) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x267b) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x267c) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x267d) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x267e) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x267f) }, /* 631x/632x */
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{ PCI_DEVICE(0x8086, 0x27b8) }, /* Gx */
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/* E
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{ PCI_DEVICE(0x8086, 0x245e) }, */
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{ PCI_DEVICE(0x8086, 0x2450) }, /* E */
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{ 0, }, /* terminate list */
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};
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MODULE_DEVICE_TABLE(pci, pci_tbl);
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static __initdata int no_fwh_detect;
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module_param(no_fwh_detect, int, 0);
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MODULE_PARM_DESC(no_fwh_detect, "Skip FWH detection:\n"
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" positive value - skip if FWH space locked read-only\n"
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" negative value - skip always");
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static inline u8 hwstatus_get(void __iomem *mem)
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{
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return readb(mem + INTEL_RNG_HW_STATUS);
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}
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static inline u8 hwstatus_set(void __iomem *mem,
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u8 hw_status)
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{
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writeb(hw_status, mem + INTEL_RNG_HW_STATUS);
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return hwstatus_get(mem);
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}
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static int intel_rng_data_present(struct hwrng *rng, int wait)
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{
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void __iomem *mem = (void __iomem *)rng->priv;
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int data, i;
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for (i = 0; i < 20; i++) {
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data = !!(readb(mem + INTEL_RNG_STATUS) &
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INTEL_RNG_DATA_PRESENT);
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if (data || !wait)
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break;
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udelay(10);
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}
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return data;
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}
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static int intel_rng_data_read(struct hwrng *rng, u32 *data)
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{
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void __iomem *mem = (void __iomem *)rng->priv;
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*data = readb(mem + INTEL_RNG_DATA);
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return 1;
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}
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static int intel_rng_init(struct hwrng *rng)
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{
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void __iomem *mem = (void __iomem *)rng->priv;
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u8 hw_status;
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int err = -EIO;
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hw_status = hwstatus_get(mem);
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/* turn RNG h/w on, if it's off */
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if ((hw_status & INTEL_RNG_ENABLED) == 0)
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hw_status = hwstatus_set(mem, hw_status | INTEL_RNG_ENABLED);
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if ((hw_status & INTEL_RNG_ENABLED) == 0) {
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pr_err(PFX "cannot enable RNG, aborting\n");
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goto out;
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}
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err = 0;
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out:
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return err;
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}
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static void intel_rng_cleanup(struct hwrng *rng)
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{
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void __iomem *mem = (void __iomem *)rng->priv;
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u8 hw_status;
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hw_status = hwstatus_get(mem);
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if (hw_status & INTEL_RNG_ENABLED)
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hwstatus_set(mem, hw_status & ~INTEL_RNG_ENABLED);
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else
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pr_warn(PFX "unusual: RNG already disabled\n");
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}
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static struct hwrng intel_rng = {
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.name = "intel",
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.init = intel_rng_init,
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.cleanup = intel_rng_cleanup,
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.data_present = intel_rng_data_present,
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.data_read = intel_rng_data_read,
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};
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struct intel_rng_hw {
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struct pci_dev *dev;
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void __iomem *mem;
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u8 bios_cntl_off;
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u8 bios_cntl_val;
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u8 fwh_dec_en1_off;
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u8 fwh_dec_en1_val;
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};
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static int __init intel_rng_hw_init(void *_intel_rng_hw)
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{
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struct intel_rng_hw *intel_rng_hw = _intel_rng_hw;
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u8 mfc, dvc;
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/* interrupts disabled in stop_machine call */
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if (!(intel_rng_hw->fwh_dec_en1_val & FWH_F8_EN_MASK))
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pci_write_config_byte(intel_rng_hw->dev,
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intel_rng_hw->fwh_dec_en1_off,
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intel_rng_hw->fwh_dec_en1_val |
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FWH_F8_EN_MASK);
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if (!(intel_rng_hw->bios_cntl_val & BIOS_CNTL_WRITE_ENABLE_MASK))
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pci_write_config_byte(intel_rng_hw->dev,
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intel_rng_hw->bios_cntl_off,
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intel_rng_hw->bios_cntl_val |
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BIOS_CNTL_WRITE_ENABLE_MASK);
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writeb(INTEL_FWH_RESET_CMD, intel_rng_hw->mem);
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writeb(INTEL_FWH_READ_ID_CMD, intel_rng_hw->mem);
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mfc = readb(intel_rng_hw->mem + INTEL_FWH_MANUFACTURER_CODE_ADDRESS);
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dvc = readb(intel_rng_hw->mem + INTEL_FWH_DEVICE_CODE_ADDRESS);
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writeb(INTEL_FWH_RESET_CMD, intel_rng_hw->mem);
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if (!(intel_rng_hw->bios_cntl_val &
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(BIOS_CNTL_LOCK_ENABLE_MASK|BIOS_CNTL_WRITE_ENABLE_MASK)))
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pci_write_config_byte(intel_rng_hw->dev,
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intel_rng_hw->bios_cntl_off,
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intel_rng_hw->bios_cntl_val);
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if (!(intel_rng_hw->fwh_dec_en1_val & FWH_F8_EN_MASK))
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pci_write_config_byte(intel_rng_hw->dev,
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intel_rng_hw->fwh_dec_en1_off,
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intel_rng_hw->fwh_dec_en1_val);
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if (mfc != INTEL_FWH_MANUFACTURER_CODE ||
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(dvc != INTEL_FWH_DEVICE_CODE_8M &&
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dvc != INTEL_FWH_DEVICE_CODE_4M)) {
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pr_notice(PFX "FWH not detected\n");
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return -ENODEV;
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}
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return 0;
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}
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static int __init intel_init_hw_struct(struct intel_rng_hw *intel_rng_hw,
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struct pci_dev *dev)
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{
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intel_rng_hw->bios_cntl_val = 0xff;
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intel_rng_hw->fwh_dec_en1_val = 0xff;
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intel_rng_hw->dev = dev;
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/* Check for Intel 82802 */
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if (dev->device < 0x2640) {
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intel_rng_hw->fwh_dec_en1_off = FWH_DEC_EN1_REG_OLD;
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intel_rng_hw->bios_cntl_off = BIOS_CNTL_REG_OLD;
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} else {
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intel_rng_hw->fwh_dec_en1_off = FWH_DEC_EN1_REG_NEW;
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intel_rng_hw->bios_cntl_off = BIOS_CNTL_REG_NEW;
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}
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pci_read_config_byte(dev, intel_rng_hw->fwh_dec_en1_off,
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&intel_rng_hw->fwh_dec_en1_val);
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pci_read_config_byte(dev, intel_rng_hw->bios_cntl_off,
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&intel_rng_hw->bios_cntl_val);
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if ((intel_rng_hw->bios_cntl_val &
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(BIOS_CNTL_LOCK_ENABLE_MASK|BIOS_CNTL_WRITE_ENABLE_MASK))
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== BIOS_CNTL_LOCK_ENABLE_MASK) {
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static __initdata /*const*/ char warning[] =
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PFX "Firmware space is locked read-only. If you can't or\n"
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PFX "don't want to disable this in firmware setup, and if\n"
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PFX "you are certain that your system has a functional\n"
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PFX "RNG, try using the 'no_fwh_detect' option.\n";
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if (no_fwh_detect)
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return -ENODEV;
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pr_warn("%s", warning);
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return -EBUSY;
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}
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intel_rng_hw->mem = ioremap_nocache(INTEL_FWH_ADDR, INTEL_FWH_ADDR_LEN);
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if (intel_rng_hw->mem == NULL)
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return -EBUSY;
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return 0;
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}
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static int __init mod_init(void)
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{
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int err = -ENODEV;
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int i;
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struct pci_dev *dev = NULL;
|
||
|
|
void __iomem *mem = mem;
|
||
|
|
u8 hw_status;
|
||
|
|
struct intel_rng_hw *intel_rng_hw;
|
||
|
|
|
||
|
|
for (i = 0; !dev && pci_tbl[i].vendor; ++i)
|
||
|
|
dev = pci_get_device(pci_tbl[i].vendor, pci_tbl[i].device,
|
||
|
|
NULL);
|
||
|
|
|
||
|
|
if (!dev)
|
||
|
|
goto out; /* Device not found. */
|
||
|
|
|
||
|
|
if (no_fwh_detect < 0) {
|
||
|
|
pci_dev_put(dev);
|
||
|
|
goto fwh_done;
|
||
|
|
}
|
||
|
|
|
||
|
|
intel_rng_hw = kmalloc(sizeof(*intel_rng_hw), GFP_KERNEL);
|
||
|
|
if (!intel_rng_hw) {
|
||
|
|
pci_dev_put(dev);
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
err = intel_init_hw_struct(intel_rng_hw, dev);
|
||
|
|
if (err) {
|
||
|
|
pci_dev_put(dev);
|
||
|
|
kfree(intel_rng_hw);
|
||
|
|
if (err == -ENODEV)
|
||
|
|
goto fwh_done;
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Since the BIOS code/data is going to disappear from its normal
|
||
|
|
* location with the Read ID command, all activity on the system
|
||
|
|
* must be stopped until the state is back to normal.
|
||
|
|
*
|
||
|
|
* Use stop_machine because IPIs can be blocked by disabling
|
||
|
|
* interrupts.
|
||
|
|
*/
|
||
|
|
err = stop_machine(intel_rng_hw_init, intel_rng_hw, NULL);
|
||
|
|
pci_dev_put(dev);
|
||
|
|
iounmap(intel_rng_hw->mem);
|
||
|
|
kfree(intel_rng_hw);
|
||
|
|
if (err)
|
||
|
|
goto out;
|
||
|
|
|
||
|
|
fwh_done:
|
||
|
|
err = -ENOMEM;
|
||
|
|
mem = ioremap(INTEL_RNG_ADDR, INTEL_RNG_ADDR_LEN);
|
||
|
|
if (!mem)
|
||
|
|
goto out;
|
||
|
|
intel_rng.priv = (unsigned long)mem;
|
||
|
|
|
||
|
|
/* Check for Random Number Generator */
|
||
|
|
err = -ENODEV;
|
||
|
|
hw_status = hwstatus_get(mem);
|
||
|
|
if ((hw_status & INTEL_RNG_PRESENT) == 0) {
|
||
|
|
iounmap(mem);
|
||
|
|
goto out;
|
||
|
|
}
|
||
|
|
|
||
|
|
pr_info("Intel 82802 RNG detected\n");
|
||
|
|
err = hwrng_register(&intel_rng);
|
||
|
|
if (err) {
|
||
|
|
pr_err(PFX "RNG registering failed (%d)\n",
|
||
|
|
err);
|
||
|
|
iounmap(mem);
|
||
|
|
}
|
||
|
|
out:
|
||
|
|
return err;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __exit mod_exit(void)
|
||
|
|
{
|
||
|
|
void __iomem *mem = (void __iomem *)intel_rng.priv;
|
||
|
|
|
||
|
|
hwrng_unregister(&intel_rng);
|
||
|
|
iounmap(mem);
|
||
|
|
}
|
||
|
|
|
||
|
|
module_init(mod_init);
|
||
|
|
module_exit(mod_exit);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("H/W RNG driver for Intel chipsets");
|
||
|
|
MODULE_LICENSE("GPL");
|