57 lines
847 B
C
57 lines
847 B
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __DRV_CLKDBG_MT6833_H
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#define __DRV_CLKDBG_MT6833_H
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enum dbg_sys_id {
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topckgen,
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infracfg_ao,
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scpsys,
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apmixed,
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apu0,
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apu1,
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apuvc,
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apuc,
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audio,
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mfgsys,
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mmsys,
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mdpsys,
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img1sys,
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img2sys,
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i2c_c,
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i2c_e,
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i2c_n,
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i2c_s,
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i2c_w,
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i2c_ws,
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infracfg,
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ipesys,
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camsys,
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cam_rawa_sys,
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cam_rawb_sys,
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pericfg,
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scp_par,
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vencsys,
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vdecsys,
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infracfg_dbg,
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infrapdn_dbg,
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dbg_sys_num,
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};
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extern void subsys_if_on(void);
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/*ram console api*/
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#ifdef CONFIG_MTK_RAM_CONSOLE
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extern void aee_rr_rec_clk(int id, u32 val);
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#endif
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extern const char * const *get_mt6833_all_clk_names(void);
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extern void print_enabled_clks_once(void);
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extern void print_subsys_reg(enum dbg_sys_id id);
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extern int get_sw_req_vcore_opp(void);
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#endif /* __DRV_CLKDBG_MT6833_H */
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