261 lines
6.5 KiB
C
261 lines
6.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017 SiFive
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* Copyright (C) 2018 Christoph Hellwig
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*/
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#define pr_fmt(fmt) "plic: " fmt
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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/*
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* This driver implements a version of the RISC-V PLIC with the actual layout
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* specified in chapter 8 of the SiFive U5 Coreplex Series Manual:
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*
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* https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf
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*
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* The largest number supported by devices marked as 'sifive,plic-1.0.0', is
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* 1024, of which device 0 is defined as non-existent by the RISC-V Privileged
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* Spec.
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*/
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#define MAX_DEVICES 1024
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#define MAX_CONTEXTS 15872
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/*
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* Each interrupt source has a priority register associated with it.
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* We always hardwire it to one in Linux.
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*/
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#define PRIORITY_BASE 0
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#define PRIORITY_PER_ID 4
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/*
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* Each hart context has a vector of interrupt enable bits associated with it.
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* There's one bit for each interrupt source.
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*/
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#define ENABLE_BASE 0x2000
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#define ENABLE_PER_HART 0x80
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/*
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* Each hart context has a set of control registers associated with it. Right
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* now there's only two: a source priority threshold over which the hart will
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* take an interrupt, and a register to claim interrupts.
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*/
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#define CONTEXT_BASE 0x200000
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#define CONTEXT_PER_HART 0x1000
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#define CONTEXT_THRESHOLD 0x00
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#define CONTEXT_CLAIM 0x04
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static void __iomem *plic_regs;
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struct plic_handler {
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bool present;
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int ctxid;
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};
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static DEFINE_PER_CPU(struct plic_handler, plic_handlers);
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static inline void __iomem *plic_hart_offset(int ctxid)
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{
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return plic_regs + CONTEXT_BASE + ctxid * CONTEXT_PER_HART;
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}
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static inline u32 __iomem *plic_enable_base(int ctxid)
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{
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return plic_regs + ENABLE_BASE + ctxid * ENABLE_PER_HART;
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}
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/*
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* Protect mask operations on the registers given that we can't assume that
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* atomic memory operations work on them.
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*/
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static DEFINE_RAW_SPINLOCK(plic_toggle_lock);
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static inline void plic_toggle(int ctxid, int hwirq, int enable)
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{
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u32 __iomem *reg = plic_enable_base(ctxid) + (hwirq / 32);
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u32 hwirq_mask = 1 << (hwirq % 32);
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raw_spin_lock(&plic_toggle_lock);
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if (enable)
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writel(readl(reg) | hwirq_mask, reg);
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else
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writel(readl(reg) & ~hwirq_mask, reg);
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raw_spin_unlock(&plic_toggle_lock);
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}
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static inline void plic_irq_toggle(struct irq_data *d, int enable)
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{
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int cpu;
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writel(enable, plic_regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID);
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for_each_cpu(cpu, irq_data_get_affinity_mask(d)) {
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struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu);
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if (handler->present)
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plic_toggle(handler->ctxid, d->hwirq, enable);
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}
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}
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static void plic_irq_enable(struct irq_data *d)
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{
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plic_irq_toggle(d, 1);
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}
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static void plic_irq_disable(struct irq_data *d)
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{
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plic_irq_toggle(d, 0);
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}
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static struct irq_chip plic_chip = {
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.name = "SiFive PLIC",
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/*
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* There is no need to mask/unmask PLIC interrupts. They are "masked"
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* by reading claim and "unmasked" when writing it back.
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*/
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.irq_enable = plic_irq_enable,
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.irq_disable = plic_irq_disable,
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};
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static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &plic_chip, handle_simple_irq);
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irq_set_chip_data(irq, NULL);
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irq_set_noprobe(irq);
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return 0;
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}
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static const struct irq_domain_ops plic_irqdomain_ops = {
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.map = plic_irqdomain_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static struct irq_domain *plic_irqdomain;
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/*
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* Handling an interrupt is a two-step process: first you claim the interrupt
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* by reading the claim register, then you complete the interrupt by writing
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* that source ID back to the same claim register. This automatically enables
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* and disables the interrupt, so there's nothing else to do.
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*/
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static void plic_handle_irq(struct pt_regs *regs)
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{
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struct plic_handler *handler = this_cpu_ptr(&plic_handlers);
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void __iomem *claim = plic_hart_offset(handler->ctxid) + CONTEXT_CLAIM;
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irq_hw_number_t hwirq;
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WARN_ON_ONCE(!handler->present);
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csr_clear(sie, SIE_SEIE);
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while ((hwirq = readl(claim))) {
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int irq = irq_find_mapping(plic_irqdomain, hwirq);
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if (unlikely(irq <= 0))
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pr_warn_ratelimited("can't find mapping for hwirq %lu\n",
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hwirq);
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else
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generic_handle_irq(irq);
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writel(hwirq, claim);
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}
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csr_set(sie, SIE_SEIE);
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}
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/*
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* Walk up the DT tree until we find an active RISC-V core (HART) node and
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* extract the cpuid from it.
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*/
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static int plic_find_hart_id(struct device_node *node)
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{
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for (; node; node = node->parent) {
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if (of_device_is_compatible(node, "riscv"))
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return riscv_of_processor_hart(node);
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}
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return -1;
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}
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static int __init plic_init(struct device_node *node,
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struct device_node *parent)
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{
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int error = 0, nr_handlers, nr_mapped = 0, i;
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u32 nr_irqs;
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if (plic_regs) {
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pr_warn("PLIC already present.\n");
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return -ENXIO;
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}
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plic_regs = of_iomap(node, 0);
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if (WARN_ON(!plic_regs))
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return -EIO;
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error = -EINVAL;
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of_property_read_u32(node, "riscv,ndev", &nr_irqs);
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if (WARN_ON(!nr_irqs))
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goto out_iounmap;
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nr_handlers = of_irq_count(node);
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if (WARN_ON(!nr_handlers))
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goto out_iounmap;
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if (WARN_ON(nr_handlers < num_possible_cpus()))
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goto out_iounmap;
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error = -ENOMEM;
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plic_irqdomain = irq_domain_add_linear(node, nr_irqs + 1,
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&plic_irqdomain_ops, NULL);
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if (WARN_ON(!plic_irqdomain))
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goto out_iounmap;
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for (i = 0; i < nr_handlers; i++) {
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struct of_phandle_args parent;
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struct plic_handler *handler;
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irq_hw_number_t hwirq;
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int cpu;
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if (of_irq_parse_one(node, i, &parent)) {
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pr_err("failed to parse parent for context %d.\n", i);
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continue;
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}
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/* skip context holes */
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if (parent.args[0] == -1)
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continue;
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cpu = plic_find_hart_id(parent.np);
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if (cpu < 0) {
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pr_warn("failed to parse hart ID for context %d.\n", i);
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continue;
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}
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handler = per_cpu_ptr(&plic_handlers, cpu);
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handler->present = true;
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handler->ctxid = i;
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/* priority must be > threshold to trigger an interrupt */
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writel(0, plic_hart_offset(i) + CONTEXT_THRESHOLD);
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for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
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plic_toggle(i, hwirq, 0);
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nr_mapped++;
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}
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pr_info("mapped %d interrupts to %d (out of %d) handlers.\n",
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nr_irqs, nr_mapped, nr_handlers);
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set_handle_irq(plic_handle_irq);
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return 0;
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out_iounmap:
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iounmap(plic_regs);
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return error;
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}
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IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init);
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IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */
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