292 lines
6.9 KiB
C
292 lines
6.9 KiB
C
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/*
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* Copyright (C) 2006 Jonathan McDowell <noodles@earth.li>
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*
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* Derived from drivers/mtd/nand/toto.c (removed in v2.6.28)
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* Copyright (c) 2003 Texas Instruments
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* Copyright (c) 2002 Thomas Gleixner <tgxl@linutronix.de>
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*
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* Converted to platform driver by Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
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* Partially stolen from plat_nand.c
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Overview:
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* This is a device driver for the NAND flash device found on the
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* Amstrad E3 (Delta).
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*/
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/rawnand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/gpio.h>
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#include <linux/platform_data/gpio-omap.h>
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#include <asm/io.h>
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#include <asm/sizes.h>
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#include <mach/board-ams-delta.h>
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#include <mach/hardware.h>
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/*
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* MTD structure for E3 (Delta)
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*/
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static struct mtd_info *ams_delta_mtd = NULL;
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/*
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* Define partitions for flash devices
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*/
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static const struct mtd_partition partition_info[] = {
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{ .name = "Kernel",
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.offset = 0,
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.size = 3 * SZ_1M + SZ_512K },
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{ .name = "u-boot",
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.offset = 3 * SZ_1M + SZ_512K,
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.size = SZ_256K },
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{ .name = "u-boot params",
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.offset = 3 * SZ_1M + SZ_512K + SZ_256K,
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.size = SZ_256K },
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{ .name = "Amstrad LDR",
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.offset = 4 * SZ_1M,
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.size = SZ_256K },
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{ .name = "File system",
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.offset = 4 * SZ_1M + 1 * SZ_256K,
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.size = 27 * SZ_1M },
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{ .name = "PBL reserved",
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.offset = 32 * SZ_1M - 3 * SZ_256K,
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.size = 3 * SZ_256K },
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};
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static void ams_delta_write_byte(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *this = mtd_to_nand(mtd);
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void __iomem *io_base = (void __iomem *)nand_get_controller_data(this);
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writew(0, io_base + OMAP_MPUIO_IO_CNTL);
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writew(byte, this->IO_ADDR_W);
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gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 0);
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ndelay(40);
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gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NWE, 1);
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}
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static u_char ams_delta_read_byte(struct mtd_info *mtd)
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{
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u_char res;
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struct nand_chip *this = mtd_to_nand(mtd);
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void __iomem *io_base = (void __iomem *)nand_get_controller_data(this);
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gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 0);
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ndelay(40);
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writew(~0, io_base + OMAP_MPUIO_IO_CNTL);
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res = readw(this->IO_ADDR_R);
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gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NRE, 1);
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return res;
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}
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static void ams_delta_write_buf(struct mtd_info *mtd, const u_char *buf,
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int len)
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{
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int i;
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for (i=0; i<len; i++)
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ams_delta_write_byte(mtd, buf[i]);
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}
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static void ams_delta_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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for (i=0; i<len; i++)
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buf[i] = ams_delta_read_byte(mtd);
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}
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/*
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* Command control function
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*
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* ctrl:
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* NAND_NCE: bit 0 -> bit 2
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* NAND_CLE: bit 1 -> bit 7
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* NAND_ALE: bit 2 -> bit 6
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*/
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static void ams_delta_hwcontrol(struct mtd_info *mtd, int cmd,
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unsigned int ctrl)
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{
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if (ctrl & NAND_CTRL_CHANGE) {
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gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_NCE,
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(ctrl & NAND_NCE) == 0);
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gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_CLE,
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(ctrl & NAND_CLE) != 0);
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gpio_set_value(AMS_DELTA_GPIO_PIN_NAND_ALE,
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(ctrl & NAND_ALE) != 0);
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}
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if (cmd != NAND_CMD_NONE)
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ams_delta_write_byte(mtd, cmd);
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}
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static int ams_delta_nand_ready(struct mtd_info *mtd)
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{
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return gpio_get_value(AMS_DELTA_GPIO_PIN_NAND_RB);
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}
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static const struct gpio _mandatory_gpio[] = {
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{
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.gpio = AMS_DELTA_GPIO_PIN_NAND_NCE,
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.flags = GPIOF_OUT_INIT_HIGH,
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.label = "nand_nce",
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},
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{
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.gpio = AMS_DELTA_GPIO_PIN_NAND_NRE,
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.flags = GPIOF_OUT_INIT_HIGH,
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.label = "nand_nre",
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},
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{
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.gpio = AMS_DELTA_GPIO_PIN_NAND_NWP,
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.flags = GPIOF_OUT_INIT_HIGH,
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.label = "nand_nwp",
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},
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{
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.gpio = AMS_DELTA_GPIO_PIN_NAND_NWE,
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.flags = GPIOF_OUT_INIT_HIGH,
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.label = "nand_nwe",
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},
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{
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.gpio = AMS_DELTA_GPIO_PIN_NAND_ALE,
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.flags = GPIOF_OUT_INIT_LOW,
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.label = "nand_ale",
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},
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{
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.gpio = AMS_DELTA_GPIO_PIN_NAND_CLE,
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.flags = GPIOF_OUT_INIT_LOW,
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.label = "nand_cle",
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},
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};
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/*
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* Main initialization routine
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*/
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static int ams_delta_init(struct platform_device *pdev)
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{
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struct nand_chip *this;
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struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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void __iomem *io_base;
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int err = 0;
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if (!res)
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return -ENXIO;
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/* Allocate memory for MTD device structure and private data */
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this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
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if (!this) {
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pr_warn("Unable to allocate E3 NAND MTD device structure.\n");
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err = -ENOMEM;
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goto out;
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}
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ams_delta_mtd = nand_to_mtd(this);
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ams_delta_mtd->owner = THIS_MODULE;
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/*
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* Don't try to request the memory region from here,
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* it should have been already requested from the
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* gpio-omap driver and requesting it again would fail.
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*/
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io_base = ioremap(res->start, resource_size(res));
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if (io_base == NULL) {
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dev_err(&pdev->dev, "ioremap failed\n");
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err = -EIO;
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goto out_free;
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}
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nand_set_controller_data(this, (void *)io_base);
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/* Set address of NAND IO lines */
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this->IO_ADDR_R = io_base + OMAP_MPUIO_INPUT_LATCH;
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this->IO_ADDR_W = io_base + OMAP_MPUIO_OUTPUT;
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this->read_byte = ams_delta_read_byte;
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this->write_buf = ams_delta_write_buf;
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this->read_buf = ams_delta_read_buf;
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this->cmd_ctrl = ams_delta_hwcontrol;
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if (gpio_request(AMS_DELTA_GPIO_PIN_NAND_RB, "nand_rdy") == 0) {
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this->dev_ready = ams_delta_nand_ready;
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} else {
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this->dev_ready = NULL;
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pr_notice("Couldn't request gpio for Delta NAND ready.\n");
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}
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/* 25 us command delay time */
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this->chip_delay = 30;
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this->ecc.mode = NAND_ECC_SOFT;
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this->ecc.algo = NAND_ECC_HAMMING;
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platform_set_drvdata(pdev, io_base);
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/* Set chip enabled, but */
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err = gpio_request_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
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if (err)
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goto out_gpio;
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/* Scan to find existence of the device */
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err = nand_scan(this, 1);
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if (err)
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goto out_mtd;
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/* Register the partitions */
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mtd_device_register(ams_delta_mtd, partition_info,
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ARRAY_SIZE(partition_info));
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goto out;
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out_mtd:
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gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
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out_gpio:
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gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
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iounmap(io_base);
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out_free:
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kfree(this);
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out:
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return err;
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}
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/*
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* Clean up routine
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*/
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static int ams_delta_cleanup(struct platform_device *pdev)
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{
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void __iomem *io_base = platform_get_drvdata(pdev);
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/* Release resources, unregister device */
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nand_release(mtd_to_nand(ams_delta_mtd));
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gpio_free_array(_mandatory_gpio, ARRAY_SIZE(_mandatory_gpio));
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gpio_free(AMS_DELTA_GPIO_PIN_NAND_RB);
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iounmap(io_base);
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/* Free the MTD device structure */
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kfree(mtd_to_nand(ams_delta_mtd));
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return 0;
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}
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static struct platform_driver ams_delta_nand_driver = {
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.probe = ams_delta_init,
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.remove = ams_delta_cleanup,
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.driver = {
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.name = "ams-delta-nand",
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},
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};
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module_platform_driver(ams_delta_nand_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Jonathan McDowell <noodles@earth.li>");
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MODULE_DESCRIPTION("Glue layer for NAND flash on Amstrad E3 (Delta)");
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