470 lines
13 KiB
C
470 lines
13 KiB
C
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/*
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Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
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Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
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Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
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Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
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Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
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Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
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Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
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Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
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<http://rt2x00.serialmonkey.com>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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/*
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Module: rt2800pci
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Abstract: rt2800pci device specific routines.
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Supported chipsets: RT2800E & RT2800ED.
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*/
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#include <linux/delay.h>
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#include <linux/etherdevice.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/eeprom_93cx6.h>
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#include "rt2x00.h"
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#include "rt2x00mmio.h"
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#include "rt2x00pci.h"
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#include "rt2800lib.h"
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#include "rt2800mmio.h"
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#include "rt2800.h"
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#include "rt2800pci.h"
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/*
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* Allow hardware encryption to be disabled.
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*/
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static bool modparam_nohwcrypt = false;
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module_param_named(nohwcrypt, modparam_nohwcrypt, bool, 0444);
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MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
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static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
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{
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return modparam_nohwcrypt;
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}
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static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
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{
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unsigned int i;
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u32 reg;
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/*
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* SOC devices don't support MCU requests.
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*/
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if (rt2x00_is_soc(rt2x00dev))
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return;
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for (i = 0; i < 200; i++) {
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reg = rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID);
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if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
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(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
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(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
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(rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
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break;
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udelay(REGISTER_BUSY_DELAY);
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}
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if (i == 200)
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rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");
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rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
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rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
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}
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static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
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{
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struct rt2x00_dev *rt2x00dev = eeprom->data;
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u32 reg;
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reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);
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eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
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eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
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eeprom->reg_data_clock =
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!!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
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eeprom->reg_chip_select =
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!!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
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}
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static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
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{
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struct rt2x00_dev *rt2x00dev = eeprom->data;
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u32 reg = 0;
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rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
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rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
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rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
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!!eeprom->reg_data_clock);
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rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
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!!eeprom->reg_chip_select);
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rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
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}
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static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
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{
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struct eeprom_93cx6 eeprom;
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u32 reg;
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reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);
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eeprom.data = rt2x00dev;
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eeprom.register_read = rt2800pci_eepromregister_read;
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eeprom.register_write = rt2800pci_eepromregister_write;
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switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
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{
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case 0:
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eeprom.width = PCI_EEPROM_WIDTH_93C46;
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break;
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case 1:
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eeprom.width = PCI_EEPROM_WIDTH_93C66;
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break;
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default:
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eeprom.width = PCI_EEPROM_WIDTH_93C86;
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break;
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}
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eeprom.reg_data_in = 0;
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eeprom.reg_data_out = 0;
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eeprom.reg_data_clock = 0;
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eeprom.reg_chip_select = 0;
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eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
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EEPROM_SIZE / sizeof(u16));
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return 0;
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}
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static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
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{
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return rt2800_efuse_detect(rt2x00dev);
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}
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static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
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{
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return rt2800_read_eeprom_efuse(rt2x00dev);
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}
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/*
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* Firmware functions
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*/
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static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
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{
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/*
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* Chip rt3290 use specific 4KB firmware named rt3290.bin.
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*/
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if (rt2x00_rt(rt2x00dev, RT3290))
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return FIRMWARE_RT3290;
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else
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return FIRMWARE_RT2860;
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}
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static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
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const u8 *data, const size_t len)
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{
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u32 reg;
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/*
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* enable Host program ram write selection
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*/
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reg = 0;
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rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
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/*
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* Write firmware to device.
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*/
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rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
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data, len);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
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rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
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rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
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rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
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return 0;
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}
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/*
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* Device state switch handlers.
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*/
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static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
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{
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int retval;
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retval = rt2800mmio_enable_radio(rt2x00dev);
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if (retval)
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return retval;
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/* After resume MCU_BOOT_SIGNAL will trash these. */
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rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
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rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
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rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
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rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
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rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
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rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
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return retval;
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}
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static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
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enum dev_state state)
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{
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if (state == STATE_AWAKE) {
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rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
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0, 0x02);
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rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
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} else if (state == STATE_SLEEP) {
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rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
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0xffffffff);
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rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
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0xffffffff);
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rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
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0xff, 0x01);
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}
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return 0;
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}
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static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
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enum dev_state state)
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{
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int retval = 0;
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switch (state) {
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case STATE_RADIO_ON:
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retval = rt2800pci_enable_radio(rt2x00dev);
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break;
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case STATE_RADIO_OFF:
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/*
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* After the radio has been disabled, the device should
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* be put to sleep for powersaving.
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*/
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rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
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break;
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case STATE_RADIO_IRQ_ON:
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case STATE_RADIO_IRQ_OFF:
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rt2800mmio_toggle_irq(rt2x00dev, state);
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break;
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case STATE_DEEP_SLEEP:
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case STATE_SLEEP:
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case STATE_STANDBY:
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case STATE_AWAKE:
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retval = rt2800pci_set_state(rt2x00dev, state);
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break;
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default:
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retval = -ENOTSUPP;
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break;
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}
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if (unlikely(retval))
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rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
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state, retval);
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return retval;
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}
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/*
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* Device probe functions.
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*/
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static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
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{
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int retval;
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if (rt2800pci_efuse_detect(rt2x00dev))
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retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
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else
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retval = rt2800pci_read_eeprom_pci(rt2x00dev);
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return retval;
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}
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static const struct ieee80211_ops rt2800pci_mac80211_ops = {
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.tx = rt2x00mac_tx,
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.start = rt2x00mac_start,
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.stop = rt2x00mac_stop,
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.add_interface = rt2x00mac_add_interface,
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.remove_interface = rt2x00mac_remove_interface,
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.config = rt2x00mac_config,
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.configure_filter = rt2x00mac_configure_filter,
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.set_key = rt2x00mac_set_key,
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.sw_scan_start = rt2x00mac_sw_scan_start,
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.sw_scan_complete = rt2x00mac_sw_scan_complete,
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.get_stats = rt2x00mac_get_stats,
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.get_key_seq = rt2800_get_key_seq,
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.set_rts_threshold = rt2800_set_rts_threshold,
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.sta_add = rt2800_sta_add,
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.sta_remove = rt2800_sta_remove,
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.bss_info_changed = rt2x00mac_bss_info_changed,
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.conf_tx = rt2800_conf_tx,
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.get_tsf = rt2800_get_tsf,
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.rfkill_poll = rt2x00mac_rfkill_poll,
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.ampdu_action = rt2800_ampdu_action,
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.flush = rt2x00mac_flush,
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.get_survey = rt2800_get_survey,
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.get_ringparam = rt2x00mac_get_ringparam,
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.tx_frames_pending = rt2x00mac_tx_frames_pending,
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};
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static const struct rt2800_ops rt2800pci_rt2800_ops = {
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.register_read = rt2x00mmio_register_read,
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.register_read_lock = rt2x00mmio_register_read, /* same for PCI */
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.register_write = rt2x00mmio_register_write,
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.register_write_lock = rt2x00mmio_register_write, /* same for PCI */
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.register_multiread = rt2x00mmio_register_multiread,
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.register_multiwrite = rt2x00mmio_register_multiwrite,
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.regbusy_read = rt2x00mmio_regbusy_read,
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.read_eeprom = rt2800pci_read_eeprom,
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.hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
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.drv_write_firmware = rt2800pci_write_firmware,
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.drv_init_registers = rt2800mmio_init_registers,
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|
|
.drv_get_txwi = rt2800mmio_get_txwi,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
|
||
|
|
.irq_handler = rt2800mmio_interrupt,
|
||
|
|
.txstatus_tasklet = rt2800mmio_txstatus_tasklet,
|
||
|
|
.pretbtt_tasklet = rt2800mmio_pretbtt_tasklet,
|
||
|
|
.tbtt_tasklet = rt2800mmio_tbtt_tasklet,
|
||
|
|
.rxdone_tasklet = rt2800mmio_rxdone_tasklet,
|
||
|
|
.autowake_tasklet = rt2800mmio_autowake_tasklet,
|
||
|
|
.probe_hw = rt2800_probe_hw,
|
||
|
|
.get_firmware_name = rt2800pci_get_firmware_name,
|
||
|
|
.check_firmware = rt2800_check_firmware,
|
||
|
|
.load_firmware = rt2800_load_firmware,
|
||
|
|
.initialize = rt2x00mmio_initialize,
|
||
|
|
.uninitialize = rt2x00mmio_uninitialize,
|
||
|
|
.get_entry_state = rt2800mmio_get_entry_state,
|
||
|
|
.clear_entry = rt2800mmio_clear_entry,
|
||
|
|
.set_device_state = rt2800pci_set_device_state,
|
||
|
|
.rfkill_poll = rt2800_rfkill_poll,
|
||
|
|
.link_stats = rt2800_link_stats,
|
||
|
|
.reset_tuner = rt2800_reset_tuner,
|
||
|
|
.link_tuner = rt2800_link_tuner,
|
||
|
|
.gain_calibration = rt2800_gain_calibration,
|
||
|
|
.vco_calibration = rt2800_vco_calibration,
|
||
|
|
.start_queue = rt2800mmio_start_queue,
|
||
|
|
.kick_queue = rt2800mmio_kick_queue,
|
||
|
|
.stop_queue = rt2800mmio_stop_queue,
|
||
|
|
.flush_queue = rt2x00mmio_flush_queue,
|
||
|
|
.write_tx_desc = rt2800mmio_write_tx_desc,
|
||
|
|
.write_tx_data = rt2800_write_tx_data,
|
||
|
|
.write_beacon = rt2800_write_beacon,
|
||
|
|
.clear_beacon = rt2800_clear_beacon,
|
||
|
|
.fill_rxdone = rt2800mmio_fill_rxdone,
|
||
|
|
.config_shared_key = rt2800_config_shared_key,
|
||
|
|
.config_pairwise_key = rt2800_config_pairwise_key,
|
||
|
|
.config_filter = rt2800_config_filter,
|
||
|
|
.config_intf = rt2800_config_intf,
|
||
|
|
.config_erp = rt2800_config_erp,
|
||
|
|
.config_ant = rt2800_config_ant,
|
||
|
|
.config = rt2800_config,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct rt2x00_ops rt2800pci_ops = {
|
||
|
|
.name = KBUILD_MODNAME,
|
||
|
|
.drv_data_size = sizeof(struct rt2800_drv_data),
|
||
|
|
.max_ap_intf = 8,
|
||
|
|
.eeprom_size = EEPROM_SIZE,
|
||
|
|
.rf_size = RF_SIZE,
|
||
|
|
.tx_queues = NUM_TX_QUEUES,
|
||
|
|
.queue_init = rt2800mmio_queue_init,
|
||
|
|
.lib = &rt2800pci_rt2x00_ops,
|
||
|
|
.drv = &rt2800pci_rt2800_ops,
|
||
|
|
.hw = &rt2800pci_mac80211_ops,
|
||
|
|
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
|
||
|
|
.debugfs = &rt2800_rt2x00debug,
|
||
|
|
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* RT2800pci module information.
|
||
|
|
*/
|
||
|
|
static const struct pci_device_id rt2800pci_device_table[] = {
|
||
|
|
{ PCI_DEVICE(0x1814, 0x0601) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x0681) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x0701) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x0781) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x3090) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x3091) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x3092) },
|
||
|
|
{ PCI_DEVICE(0x1432, 0x7708) },
|
||
|
|
{ PCI_DEVICE(0x1432, 0x7727) },
|
||
|
|
{ PCI_DEVICE(0x1432, 0x7728) },
|
||
|
|
{ PCI_DEVICE(0x1432, 0x7738) },
|
||
|
|
{ PCI_DEVICE(0x1432, 0x7748) },
|
||
|
|
{ PCI_DEVICE(0x1432, 0x7758) },
|
||
|
|
{ PCI_DEVICE(0x1432, 0x7768) },
|
||
|
|
{ PCI_DEVICE(0x1462, 0x891a) },
|
||
|
|
{ PCI_DEVICE(0x1a3b, 0x1059) },
|
||
|
|
#ifdef CONFIG_RT2800PCI_RT3290
|
||
|
|
{ PCI_DEVICE(0x1814, 0x3290) },
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_RT2800PCI_RT33XX
|
||
|
|
{ PCI_DEVICE(0x1814, 0x3390) },
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_RT2800PCI_RT35XX
|
||
|
|
{ PCI_DEVICE(0x1432, 0x7711) },
|
||
|
|
{ PCI_DEVICE(0x1432, 0x7722) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x3060) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x3062) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x3562) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x3592) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x3593) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x359f) },
|
||
|
|
#endif
|
||
|
|
#ifdef CONFIG_RT2800PCI_RT53XX
|
||
|
|
{ PCI_DEVICE(0x1814, 0x5360) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x5362) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x5390) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x5392) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x539a) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x539b) },
|
||
|
|
{ PCI_DEVICE(0x1814, 0x539f) },
|
||
|
|
#endif
|
||
|
|
{ 0, }
|
||
|
|
};
|
||
|
|
|
||
|
|
MODULE_AUTHOR(DRV_PROJECT);
|
||
|
|
MODULE_VERSION(DRV_VERSION);
|
||
|
|
MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
|
||
|
|
MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
|
||
|
|
MODULE_FIRMWARE(FIRMWARE_RT2860);
|
||
|
|
MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
|
||
|
|
MODULE_LICENSE("GPL");
|
||
|
|
|
||
|
|
static int rt2800pci_probe(struct pci_dev *pci_dev,
|
||
|
|
const struct pci_device_id *id)
|
||
|
|
{
|
||
|
|
return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct pci_driver rt2800pci_driver = {
|
||
|
|
.name = KBUILD_MODNAME,
|
||
|
|
.id_table = rt2800pci_device_table,
|
||
|
|
.probe = rt2800pci_probe,
|
||
|
|
.remove = rt2x00pci_remove,
|
||
|
|
.suspend = rt2x00pci_suspend,
|
||
|
|
.resume = rt2x00pci_resume,
|
||
|
|
};
|
||
|
|
|
||
|
|
module_pci_driver(rt2800pci_driver);
|