439 lines
15 KiB
C
439 lines
15 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/************************************************************************
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* Copyright 2003 Digi International (www.digi.com)
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*
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* Copyright (C) 2004 IBM Corporation. All rights reserved.
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*
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* Contact Information:
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* Scott H Kilau <Scott_Kilau@digi.com>
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* Wendy Xiong <wendyx@us.ibm.com>
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*
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***********************************************************************/
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#ifndef __JSM_DRIVER_H
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#define __JSM_DRIVER_H
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#include <linux/kernel.h>
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#include <linux/types.h> /* To pick up the varions Linux types */
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#include <linux/tty.h>
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#include <linux/serial_core.h>
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#include <linux/device.h>
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/*
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* Debugging levels can be set using debug insmod variable
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* They can also be compiled out completely.
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*/
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enum {
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DBG_INIT = 0x01,
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DBG_BASIC = 0x02,
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DBG_CORE = 0x04,
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DBG_OPEN = 0x08,
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DBG_CLOSE = 0x10,
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DBG_READ = 0x20,
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DBG_WRITE = 0x40,
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DBG_IOCTL = 0x80,
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DBG_PROC = 0x100,
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DBG_PARAM = 0x200,
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DBG_PSCAN = 0x400,
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DBG_EVENT = 0x800,
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DBG_DRAIN = 0x1000,
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DBG_MSIGS = 0x2000,
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DBG_MGMT = 0x4000,
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DBG_INTR = 0x8000,
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DBG_CARR = 0x10000,
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};
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#define jsm_dbg(nlevel, pdev, fmt, ...) \
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do { \
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if (DBG_##nlevel & jsm_debug) \
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dev_dbg(pdev->dev, fmt, ##__VA_ARGS__); \
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} while (0)
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#define MAXLINES 256
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#define MAXPORTS 8
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#define MAX_STOPS_SENT 5
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/* Board ids */
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#define PCI_DEVICE_ID_CLASSIC_4 0x0028
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#define PCI_DEVICE_ID_CLASSIC_8 0x0029
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#define PCI_DEVICE_ID_CLASSIC_4_422 0x00D0
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#define PCI_DEVICE_ID_CLASSIC_8_422 0x00D1
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#define PCI_DEVICE_ID_NEO_4 0x00B0
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#define PCI_DEVICE_ID_NEO_1_422 0x00CC
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#define PCI_DEVICE_ID_NEO_1_422_485 0x00CD
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#define PCI_DEVICE_ID_NEO_2_422_485 0x00CE
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#define PCIE_DEVICE_ID_NEO_8 0x00F0
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#define PCIE_DEVICE_ID_NEO_4 0x00F1
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#define PCIE_DEVICE_ID_NEO_4RJ45 0x00F2
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#define PCIE_DEVICE_ID_NEO_8RJ45 0x00F3
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/* Board type definitions */
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#define T_NEO 0000
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#define T_CLASSIC 0001
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#define T_PCIBUS 0400
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/* Board State Definitions */
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#define BD_RUNNING 0x0
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#define BD_REASON 0x7f
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#define BD_NOTFOUND 0x1
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#define BD_NOIOPORT 0x2
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#define BD_NOMEM 0x3
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#define BD_NOBIOS 0x4
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#define BD_NOFEP 0x5
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#define BD_FAILED 0x6
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#define BD_ALLOCATED 0x7
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#define BD_TRIBOOT 0x8
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#define BD_BADKME 0x80
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/* 4 extra for alignment play space */
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#define WRITEBUFLEN ((4096) + 4)
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#define JSM_VERSION "jsm: 1.2-1-INKERNEL"
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#define JSM_PARTNUM "40002438_A-INKERNEL"
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struct jsm_board;
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struct jsm_channel;
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/************************************************************************
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* Per board operations structure *
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************************************************************************/
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struct board_ops {
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irq_handler_t intr;
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void (*uart_init)(struct jsm_channel *ch);
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void (*uart_off)(struct jsm_channel *ch);
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void (*param)(struct jsm_channel *ch);
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void (*assert_modem_signals)(struct jsm_channel *ch);
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void (*flush_uart_write)(struct jsm_channel *ch);
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void (*flush_uart_read)(struct jsm_channel *ch);
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void (*disable_receiver)(struct jsm_channel *ch);
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void (*enable_receiver)(struct jsm_channel *ch);
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void (*send_break)(struct jsm_channel *ch);
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void (*clear_break)(struct jsm_channel *ch);
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void (*send_start_character)(struct jsm_channel *ch);
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void (*send_stop_character)(struct jsm_channel *ch);
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void (*copy_data_from_queue_to_uart)(struct jsm_channel *ch);
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u32 (*get_uart_bytes_left)(struct jsm_channel *ch);
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void (*send_immediate_char)(struct jsm_channel *ch, unsigned char);
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};
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/*
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* Per-board information
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*/
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struct jsm_board
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{
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int boardnum; /* Board number: 0-32 */
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int type; /* Type of board */
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u8 rev; /* PCI revision ID */
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struct pci_dev *pci_dev;
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u32 maxports; /* MAX ports this board can handle */
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spinlock_t bd_intr_lock; /* Used to protect the poller tasklet and
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* the interrupt routine from each other.
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*/
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u32 nasync; /* Number of ports on card */
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u32 irq; /* Interrupt request number */
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u64 membase; /* Start of base memory of the card */
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u64 membase_end; /* End of base memory of the card */
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u8 __iomem *re_map_membase;/* Remapped memory of the card */
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u64 iobase; /* Start of io base of the card */
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u64 iobase_end; /* End of io base of the card */
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u32 bd_uart_offset; /* Space between each UART */
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struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */
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u32 bd_dividend; /* Board/UARTs specific dividend */
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struct board_ops *bd_ops;
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struct list_head jsm_board_entry;
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};
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/************************************************************************
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* Device flag definitions for ch_flags.
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************************************************************************/
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#define CH_PRON 0x0001 /* Printer on string */
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#define CH_STOP 0x0002 /* Output is stopped */
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#define CH_STOPI 0x0004 /* Input is stopped */
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#define CH_CD 0x0008 /* Carrier is present */
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#define CH_FCAR 0x0010 /* Carrier forced on */
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#define CH_HANGUP 0x0020 /* Hangup received */
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#define CH_RECEIVER_OFF 0x0040 /* Receiver is off */
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#define CH_OPENING 0x0080 /* Port in fragile open state */
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#define CH_CLOSING 0x0100 /* Port in fragile close state */
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#define CH_FIFO_ENABLED 0x0200 /* Port has FIFOs enabled */
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#define CH_TX_FIFO_EMPTY 0x0400 /* TX Fifo is completely empty */
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#define CH_TX_FIFO_LWM 0x0800 /* TX Fifo is below Low Water */
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#define CH_BREAK_SENDING 0x1000 /* Break is being sent */
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#define CH_LOOPBACK 0x2000 /* Channel is in lookback mode */
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#define CH_BAUD0 0x08000 /* Used for checking B0 transitions */
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/* Our Read/Error queue sizes */
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#define RQUEUEMASK 0x1FFF /* 8 K - 1 */
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#define EQUEUEMASK 0x1FFF /* 8 K - 1 */
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#define RQUEUESIZE (RQUEUEMASK + 1)
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#define EQUEUESIZE RQUEUESIZE
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/************************************************************************
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* Channel information structure.
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************************************************************************/
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struct jsm_channel {
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struct uart_port uart_port;
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struct jsm_board *ch_bd; /* Board structure pointer */
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spinlock_t ch_lock; /* provide for serialization */
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wait_queue_head_t ch_flags_wait;
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u32 ch_portnum; /* Port number, 0 offset. */
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u32 ch_open_count; /* open count */
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u32 ch_flags; /* Channel flags */
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u64 ch_close_delay; /* How long we should drop RTS/DTR for */
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tcflag_t ch_c_iflag; /* channel iflags */
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tcflag_t ch_c_cflag; /* channel cflags */
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tcflag_t ch_c_oflag; /* channel oflags */
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tcflag_t ch_c_lflag; /* channel lflags */
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u8 ch_stopc; /* Stop character */
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u8 ch_startc; /* Start character */
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u8 ch_mostat; /* FEP output modem status */
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u8 ch_mistat; /* FEP input modem status */
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/* Pointers to the "mapped" UART structs */
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struct neo_uart_struct __iomem *ch_neo_uart; /* NEO card */
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struct cls_uart_struct __iomem *ch_cls_uart; /* Classic card */
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u8 ch_cached_lsr; /* Cached value of the LSR register */
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u8 *ch_rqueue; /* Our read queue buffer - malloc'ed */
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u16 ch_r_head; /* Head location of the read queue */
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u16 ch_r_tail; /* Tail location of the read queue */
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u8 *ch_equeue; /* Our error queue buffer - malloc'ed */
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u16 ch_e_head; /* Head location of the error queue */
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u16 ch_e_tail; /* Tail location of the error queue */
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u64 ch_rxcount; /* total of data received so far */
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u64 ch_txcount; /* total of data transmitted so far */
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u8 ch_r_tlevel; /* Receive Trigger level */
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u8 ch_t_tlevel; /* Transmit Trigger level */
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u8 ch_r_watermark; /* Receive Watermark */
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u32 ch_stops_sent; /* How many times I have sent a stop character
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* to try to stop the other guy sending.
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*/
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u64 ch_err_parity; /* Count of parity errors on channel */
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u64 ch_err_frame; /* Count of framing errors on channel */
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u64 ch_err_break; /* Count of breaks on channel */
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u64 ch_err_overrun; /* Count of overruns on channel */
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u64 ch_xon_sends; /* Count of xons transmitted */
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u64 ch_xoff_sends; /* Count of xoffs transmitted */
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};
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/************************************************************************
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* Per channel/port Classic UART structures *
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************************************************************************
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* Base Structure Entries Usage Meanings to Host *
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* *
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* W = read write R = read only *
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* U = Unused. *
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************************************************************************/
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struct cls_uart_struct {
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u8 txrx; /* WR RHR/THR - Holding Reg */
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u8 ier; /* WR IER - Interrupt Enable Reg */
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u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg*/
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u8 lcr; /* WR LCR - Line Control Reg */
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u8 mcr; /* WR MCR - Modem Control Reg */
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u8 lsr; /* WR LSR - Line Status Reg */
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u8 msr; /* WR MSR - Modem Status Reg */
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u8 spr; /* WR SPR - Scratch Pad Reg */
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};
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/* Where to read the interrupt register (8bits) */
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#define UART_CLASSIC_POLL_ADDR_OFFSET 0x40
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#define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
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#define UART_16654_FCR_TXTRIGGER_8 0x0
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#define UART_16654_FCR_TXTRIGGER_16 0x10
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#define UART_16654_FCR_TXTRIGGER_32 0x20
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#define UART_16654_FCR_TXTRIGGER_56 0x30
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#define UART_16654_FCR_RXTRIGGER_8 0x0
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#define UART_16654_FCR_RXTRIGGER_16 0x40
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#define UART_16654_FCR_RXTRIGGER_56 0x80
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#define UART_16654_FCR_RXTRIGGER_60 0xC0
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#define UART_IIR_CTSRTS 0x20 /* Received CTS/RTS change of state */
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#define UART_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
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/*
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* These are the EXTENDED definitions for the Exar 654's Interrupt
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* Enable Register.
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*/
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#define UART_EXAR654_EFR_ECB 0x10 /* Enhanced control bit */
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#define UART_EXAR654_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
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#define UART_EXAR654_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
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#define UART_EXAR654_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
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#define UART_EXAR654_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
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#define UART_EXAR654_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
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#define UART_EXAR654_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
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#define UART_EXAR654_IER_XOFF 0x20 /* Xoff Interrupt Enable */
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#define UART_EXAR654_IER_RTSDTR 0x40 /* Output Interrupt Enable */
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#define UART_EXAR654_IER_CTSDSR 0x80 /* Input Interrupt Enable */
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/************************************************************************
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* Per channel/port NEO UART structure *
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************************************************************************
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* Base Structure Entries Usage Meanings to Host *
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* *
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* W = read write R = read only *
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* U = Unused. *
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************************************************************************/
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struct neo_uart_struct {
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u8 txrx; /* WR RHR/THR - Holding Reg */
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u8 ier; /* WR IER - Interrupt Enable Reg */
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u8 isr_fcr; /* WR ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
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u8 lcr; /* WR LCR - Line Control Reg */
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u8 mcr; /* WR MCR - Modem Control Reg */
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u8 lsr; /* WR LSR - Line Status Reg */
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u8 msr; /* WR MSR - Modem Status Reg */
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u8 spr; /* WR SPR - Scratch Pad Reg */
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u8 fctr; /* WR FCTR - Feature Control Reg */
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u8 efr; /* WR EFR - Enhanced Function Reg */
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u8 tfifo; /* WR TXCNT/TXTRG - Transmit FIFO Reg */
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u8 rfifo; /* WR RXCNT/RXTRG - Receive FIFO Reg */
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u8 xoffchar1; /* WR XOFF 1 - XOff Character 1 Reg */
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u8 xoffchar2; /* WR XOFF 2 - XOff Character 2 Reg */
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u8 xonchar1; /* WR XON 1 - Xon Character 1 Reg */
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u8 xonchar2; /* WR XON 2 - XOn Character 2 Reg */
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u8 reserved1[0x2ff - 0x200]; /* U Reserved by Exar */
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u8 txrxburst[64]; /* RW 64 bytes of RX/TX FIFO Data */
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u8 reserved2[0x37f - 0x340]; /* U Reserved by Exar */
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u8 rxburst_with_errors[64]; /* R 64 bytes of RX FIFO Data + LSR */
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};
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/* Where to read the extended interrupt register (32bits instead of 8bits) */
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#define UART_17158_POLL_ADDR_OFFSET 0x80
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/*
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* These are the redefinitions for the FCTR on the XR17C158, since
|
||
|
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* Exar made them different than their earlier design. (XR16C854)
|
||
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|
*/
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|
||
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/* These are only applicable when table D is selected */
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#define UART_17158_FCTR_RTS_NODELAY 0x00
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#define UART_17158_FCTR_RTS_4DELAY 0x01
|
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#define UART_17158_FCTR_RTS_6DELAY 0x02
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#define UART_17158_FCTR_RTS_8DELAY 0x03
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#define UART_17158_FCTR_RTS_12DELAY 0x12
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||
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#define UART_17158_FCTR_RTS_16DELAY 0x05
|
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#define UART_17158_FCTR_RTS_20DELAY 0x13
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#define UART_17158_FCTR_RTS_24DELAY 0x06
|
||
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#define UART_17158_FCTR_RTS_28DELAY 0x14
|
||
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#define UART_17158_FCTR_RTS_32DELAY 0x07
|
||
|
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#define UART_17158_FCTR_RTS_36DELAY 0x16
|
||
|
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#define UART_17158_FCTR_RTS_40DELAY 0x08
|
||
|
|
#define UART_17158_FCTR_RTS_44DELAY 0x09
|
||
|
|
#define UART_17158_FCTR_RTS_48DELAY 0x10
|
||
|
|
#define UART_17158_FCTR_RTS_52DELAY 0x11
|
||
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|
||
|
|
#define UART_17158_FCTR_RTS_IRDA 0x10
|
||
|
|
#define UART_17158_FCTR_RS485 0x20
|
||
|
|
#define UART_17158_FCTR_TRGA 0x00
|
||
|
|
#define UART_17158_FCTR_TRGB 0x40
|
||
|
|
#define UART_17158_FCTR_TRGC 0x80
|
||
|
|
#define UART_17158_FCTR_TRGD 0xC0
|
||
|
|
|
||
|
|
/* 17158 trigger table selects.. */
|
||
|
|
#define UART_17158_FCTR_BIT6 0x40
|
||
|
|
#define UART_17158_FCTR_BIT7 0x80
|
||
|
|
|
||
|
|
/* 17158 TX/RX memmapped buffer offsets */
|
||
|
|
#define UART_17158_RX_FIFOSIZE 64
|
||
|
|
#define UART_17158_TX_FIFOSIZE 64
|
||
|
|
|
||
|
|
/* 17158 Extended IIR's */
|
||
|
|
#define UART_17158_IIR_RDI_TIMEOUT 0x0C /* Receiver data TIMEOUT */
|
||
|
|
#define UART_17158_IIR_XONXOFF 0x10 /* Received an XON/XOFF char */
|
||
|
|
#define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */
|
||
|
|
#define UART_17158_IIR_FIFO_ENABLED 0xC0 /* 16550 FIFOs are Enabled */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* These are the extended interrupts that get sent
|
||
|
|
* back to us from the UART's 32bit interrupt register
|
||
|
|
*/
|
||
|
|
#define UART_17158_RX_LINE_STATUS 0x1 /* RX Ready */
|
||
|
|
#define UART_17158_RXRDY_TIMEOUT 0x2 /* RX Ready Timeout */
|
||
|
|
#define UART_17158_TXRDY 0x3 /* TX Ready */
|
||
|
|
#define UART_17158_MSR 0x4 /* Modem State Change */
|
||
|
|
#define UART_17158_TX_AND_FIFO_CLR 0x40 /* Transmitter Holding Reg Empty */
|
||
|
|
#define UART_17158_RX_FIFO_DATA_ERROR 0x80 /* UART detected an RX FIFO Data error */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* These are the EXTENDED definitions for the 17C158's Interrupt
|
||
|
|
* Enable Register.
|
||
|
|
*/
|
||
|
|
#define UART_17158_EFR_ECB 0x10 /* Enhanced control bit */
|
||
|
|
#define UART_17158_EFR_IXON 0x2 /* Receiver compares Xon1/Xoff1 */
|
||
|
|
#define UART_17158_EFR_IXOFF 0x8 /* Transmit Xon1/Xoff1 */
|
||
|
|
#define UART_17158_EFR_RTSDTR 0x40 /* Auto RTS/DTR Flow Control Enable */
|
||
|
|
#define UART_17158_EFR_CTSDSR 0x80 /* Auto CTS/DSR Flow COntrol Enable */
|
||
|
|
|
||
|
|
#define UART_17158_XOFF_DETECT 0x1 /* Indicates whether chip saw an incoming XOFF char */
|
||
|
|
#define UART_17158_XON_DETECT 0x2 /* Indicates whether chip saw an incoming XON char */
|
||
|
|
|
||
|
|
#define UART_17158_IER_RSVD1 0x10 /* Reserved by Exar */
|
||
|
|
#define UART_17158_IER_XOFF 0x20 /* Xoff Interrupt Enable */
|
||
|
|
#define UART_17158_IER_RTSDTR 0x40 /* Output Interrupt Enable */
|
||
|
|
#define UART_17158_IER_CTSDSR 0x80 /* Input Interrupt Enable */
|
||
|
|
|
||
|
|
#define PCI_DEVICE_NEO_2DB9_PCI_NAME "Neo 2 - DB9 Universal PCI"
|
||
|
|
#define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME "Neo 2 - DB9 Universal PCI - Powered Ring Indicator"
|
||
|
|
#define PCI_DEVICE_NEO_2RJ45_PCI_NAME "Neo 2 - RJ45 Universal PCI"
|
||
|
|
#define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator"
|
||
|
|
#define PCIE_DEVICE_NEO_IBM_PCI_NAME "Neo 4 - PCI Express - IBM"
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Our Global Variables.
|
||
|
|
*/
|
||
|
|
extern struct uart_driver jsm_uart_driver;
|
||
|
|
extern struct board_ops jsm_neo_ops;
|
||
|
|
extern struct board_ops jsm_cls_ops;
|
||
|
|
extern int jsm_debug;
|
||
|
|
|
||
|
|
/*************************************************************************
|
||
|
|
*
|
||
|
|
* Prototypes for non-static functions used in more than one module
|
||
|
|
*
|
||
|
|
*************************************************************************/
|
||
|
|
int jsm_tty_init(struct jsm_board *);
|
||
|
|
int jsm_uart_port_init(struct jsm_board *);
|
||
|
|
int jsm_remove_uart_port(struct jsm_board *);
|
||
|
|
void jsm_input(struct jsm_channel *ch);
|
||
|
|
void jsm_check_queue_flow_control(struct jsm_channel *ch);
|
||
|
|
|
||
|
|
#endif
|