214 lines
8.3 KiB
Plaintext
214 lines
8.3 KiB
Plaintext
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* Rockchip rk3399 DMC (Dynamic Memory Controller) device
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Required properties:
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- compatible: Must be "rockchip,rk3399-dmc".
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- devfreq-events: Node to get DDR loading, Refer to
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Documentation/devicetree/bindings/devfreq/event/
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rockchip-dfi.txt
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- clocks: Phandles for clock specified in "clock-names" property
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- clock-names : The name of clock used by the DFI, must be
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"pclk_ddr_mon";
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- operating-points-v2: Refer to Documentation/devicetree/bindings/opp/opp.txt
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for details.
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- center-supply: DMC supply node.
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- status: Marks the node enabled/disabled.
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Optional properties:
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- interrupts: The CPU interrupt number. The interrupt specifier
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format depends on the interrupt controller.
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It should be a DCF interrupt. When DDR DVFS finishes
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a DCF interrupt is triggered.
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Following properties relate to DDR timing:
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- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/rk3399-ddr.h,
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it selects the DDR3 cl-trp-trcd type. It must be
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set according to "Speed Bin" in DDR3 datasheet,
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DO NOT use a smaller "Speed Bin" than specified
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for the DDR3 being used.
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- rockchip,pd_idle : Configure the PD_IDLE value. Defines the
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power-down idle period in which memories are
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placed into power-down mode if bus is idle
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for PD_IDLE DFI clock cycles.
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- rockchip,sr_idle : Configure the SR_IDLE value. Defines the
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self-refresh idle period in which memories are
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placed into self-refresh mode if bus is idle
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for SR_IDLE * 1024 DFI clock cycles (DFI
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clocks freq is half of DRAM clock), default
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value is "0".
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- rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller
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clock gating idle period. Memories are placed
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into self-refresh mode and memory controller
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clock arg gating started if bus is idle for
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sr_mc_gate_idle*1024 DFI clock cycles.
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- rockchip,srpd_lite_idle : Defines the self-refresh power down idle
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period in which memories are placed into
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self-refresh power down mode if bus is idle
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for srpd_lite_idle * 1024 DFI clock cycles.
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This parameter is for LPDDR4 only.
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- rockchip,standby_idle : Defines the standby idle period in which
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memories are placed into self-refresh mode.
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The controller, pi, PHY and DRAM clock will
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be gated if bus is idle for standby_idle * DFI
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clock cycles.
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- rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
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When DDR frequency is less than DRAM_DLL_DISB_FREQ,
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DDR3 DLL will be bypassed. Note: if DLL was bypassed,
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the odt will also stop working.
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- rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in
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MHz (Mega Hz). When DDR frequency is less than
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DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
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Note: PHY DLL and PHY ODT are independent.
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- rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
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the ODT disable frequency in MHz (Mega Hz).
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when the DDR frequency is less then ddr3_odt_dis_freq,
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the ODT on the DRAM side and controller side are
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both disabled.
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- rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
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the DRAM side driver strength in ohms. Default
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value is DDR3_DS_40ohm.
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- rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
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the DRAM side ODT strength in ohms. Default value
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is DDR3_ODT_120ohm.
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- rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
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the phy side CA line (incluing command line,
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address line and clock line) driver strength.
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Default value is PHY_DRV_ODT_40.
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- rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
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the PHY side DQ line (including DQS/DQ/DM line)
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driver strength. Default value is PHY_DRV_ODT_40.
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- rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
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the PHY side ODT strength. Default value is
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PHY_DRV_ODT_240.
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- rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
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then ODT disable frequency in MHz (Mega Hz).
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When DDR frequency is less then ddr3_odt_dis_freq,
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the ODT on the DRAM side and controller side are
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both disabled.
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- rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
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the DRAM side driver strength in ohms. Default
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value is LP3_DS_34ohm.
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- rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
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the DRAM side ODT strength in ohms. Default value
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is LP3_ODT_240ohm.
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- rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
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the PHY side CA line (including command line,
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address line and clock line) driver strength.
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Default value is PHY_DRV_ODT_40.
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- rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
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the PHY side DQ line (including DQS/DQ/DM line)
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driver strength. Default value is
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PHY_DRV_ODT_40.
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- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
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the phy side odt strength, default value is
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PHY_DRV_ODT_240.
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- rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
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defines the ODT disable frequency in
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MHz (Mega Hz). When the DDR frequency is less then
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ddr3_odt_dis_freq, the ODT on the DRAM side and
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controller side are both disabled.
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- rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
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the DRAM side driver strength in ohms. Default
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value is LP4_PDDS_60ohm.
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- rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
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the DRAM side ODT on DQS/DQ line strength in ohms.
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Default value is LP4_DQ_ODT_40ohm.
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- rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
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the DRAM side ODT on CA line strength in ohms.
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Default value is LP4_CA_ODT_40ohm.
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- rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
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the PHY side CA line (including command address
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line) driver strength. Default value is
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PHY_DRV_ODT_40.
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- rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
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the PHY side clock line and CS line driver
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strength. Default value is PHY_DRV_ODT_80.
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- rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
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the PHY side DQ line (including DQS/DQ/DM line)
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driver strength. Default value is PHY_DRV_ODT_80.
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- rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
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the PHY side ODT strength. Default value is
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PHY_DRV_ODT_60.
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Example:
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dmc_opp_table: dmc_opp_table {
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compatible = "operating-points-v2";
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opp00 {
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opp-hz = /bits/ 64 <300000000>;
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opp-microvolt = <900000>;
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};
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opp01 {
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opp-hz = /bits/ 64 <666000000>;
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opp-microvolt = <900000>;
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};
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};
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dmc: dmc {
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compatible = "rockchip,rk3399-dmc";
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devfreq-events = <&dfi>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_DDRCLK>;
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clock-names = "dmc_clk";
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operating-points-v2 = <&dmc_opp_table>;
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center-supply = <&ppvar_centerlogic>;
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upthreshold = <15>;
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downdifferential = <10>;
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rockchip,ddr3_speed_bin = <21>;
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rockchip,pd_idle = <0x40>;
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rockchip,sr_idle = <0x2>;
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rockchip,sr_mc_gate_idle = <0x3>;
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rockchip,srpd_lite_idle = <0x4>;
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rockchip,standby_idle = <0x2000>;
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rockchip,dram_dll_dis_freq = <300>;
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rockchip,phy_dll_dis_freq = <125>;
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rockchip,auto_pd_dis_freq = <666>;
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rockchip,ddr3_odt_dis_freq = <333>;
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rockchip,ddr3_drv = <DDR3_DS_40ohm>;
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rockchip,ddr3_odt = <DDR3_ODT_120ohm>;
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rockchip,phy_ddr3_ca_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_ddr3_dq_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_ddr3_odt = <PHY_DRV_ODT_240>;
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rockchip,lpddr3_odt_dis_freq = <333>;
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rockchip,lpddr3_drv = <LP3_DS_34ohm>;
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rockchip,lpddr3_odt = <LP3_ODT_240ohm>;
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rockchip,phy_lpddr3_ca_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_lpddr3_dq_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_lpddr3_odt = <PHY_DRV_ODT_240>;
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rockchip,lpddr4_odt_dis_freq = <333>;
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rockchip,lpddr4_drv = <LP4_PDDS_60ohm>;
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rockchip,lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
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rockchip,lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
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rockchip,phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>;
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rockchip,phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>;
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rockchip,phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>;
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rockchip,phy_lpddr4_odt = <PHY_DRV_ODT_60>;
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};
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