106 lines
2.9 KiB
C
106 lines
2.9 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/***************************************************************************/
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/*
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* m54xx.c -- platform support for ColdFire 54xx based boards
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*
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* Copyright (C) 2010, Philippe De Muyter <phdm@macqel.be>
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*/
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/***************************************************************************/
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#include <linux/kernel.h>
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#include <linux/param.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/clk.h>
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#include <linux/bootmem.h>
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#include <asm/pgalloc.h>
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#include <asm/machdep.h>
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#include <asm/coldfire.h>
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#include <asm/m54xxsim.h>
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#include <asm/mcfuart.h>
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#include <asm/mcfclk.h>
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#include <asm/m54xxgpt.h>
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#ifdef CONFIG_MMU
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#include <asm/mmu_context.h>
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#endif
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/***************************************************************************/
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DEFINE_CLK(pll, "pll.0", MCF_CLK);
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DEFINE_CLK(sys, "sys.0", MCF_BUSCLK);
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DEFINE_CLK(mcfslt0, "mcfslt.0", MCF_BUSCLK);
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DEFINE_CLK(mcfslt1, "mcfslt.1", MCF_BUSCLK);
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DEFINE_CLK(mcfuart0, "mcfuart.0", MCF_BUSCLK);
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DEFINE_CLK(mcfuart1, "mcfuart.1", MCF_BUSCLK);
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DEFINE_CLK(mcfuart2, "mcfuart.2", MCF_BUSCLK);
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DEFINE_CLK(mcfuart3, "mcfuart.3", MCF_BUSCLK);
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DEFINE_CLK(mcfi2c0, "imx1-i2c.0", MCF_BUSCLK);
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struct clk *mcf_clks[] = {
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&clk_pll,
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&clk_sys,
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&clk_mcfslt0,
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&clk_mcfslt1,
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&clk_mcfuart0,
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&clk_mcfuart1,
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&clk_mcfuart2,
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&clk_mcfuart3,
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&clk_mcfi2c0,
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NULL
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};
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/***************************************************************************/
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static void __init m54xx_uarts_init(void)
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{
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/* enable io pins */
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__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC0);
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__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS,
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MCFGPIO_PAR_PSC1);
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__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD | MCF_PAR_PSC_RTS_RTS |
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MCF_PAR_PSC_CTS_CTS, MCFGPIO_PAR_PSC2);
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__raw_writeb(MCF_PAR_PSC_TXD | MCF_PAR_PSC_RXD, MCFGPIO_PAR_PSC3);
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}
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/***************************************************************************/
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static void __init m54xx_i2c_init(void)
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{
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#if IS_ENABLED(CONFIG_I2C_IMX)
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u32 r;
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/* set the fec/i2c/irq pin assignment register for i2c */
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r = readl(MCF_PAR_FECI2CIRQ);
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r |= MCF_PAR_FECI2CIRQ_SDA | MCF_PAR_FECI2CIRQ_SCL;
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writel(r, MCF_PAR_FECI2CIRQ);
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#endif /* IS_ENABLED(CONFIG_I2C_IMX) */
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}
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/***************************************************************************/
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static void mcf54xx_reset(void)
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{
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/* disable interrupts and enable the watchdog */
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asm("movew #0x2700, %sr\n");
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__raw_writel(0, MCF_GPT_GMS0);
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__raw_writel(MCF_GPT_GCIR_CNT(1), MCF_GPT_GCIR0);
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__raw_writel(MCF_GPT_GMS_WDEN | MCF_GPT_GMS_CE | MCF_GPT_GMS_TMS(4),
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MCF_GPT_GMS0);
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}
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/***************************************************************************/
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void __init config_BSP(char *commandp, int size)
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{
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mach_reset = mcf54xx_reset;
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mach_sched_init = hw_timer_init;
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m54xx_uarts_init();
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m54xx_i2c_init();
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}
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/***************************************************************************/
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