346 lines
7.8 KiB
C
346 lines
7.8 KiB
C
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/*
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* IEEE754 floating point arithmetic
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* double precision: MADDF.f (Fused Multiply Add)
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* MADDF.fmt: FPR[fd] = FPR[fd] + (FPR[fs] x FPR[ft])
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*
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* MIPS floating point support
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* Copyright (C) 2015 Imagination Technologies, Ltd.
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* Author: Markos Chandras <markos.chandras@imgtec.com>
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*
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* This program is free software; you can distribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; version 2 of the License.
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*/
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#include "ieee754dp.h"
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/* 128 bits shift right logical with rounding. */
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static void srl128(u64 *hptr, u64 *lptr, int count)
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{
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u64 low;
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if (count >= 128) {
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*lptr = *hptr != 0 || *lptr != 0;
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*hptr = 0;
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} else if (count >= 64) {
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if (count == 64) {
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*lptr = *hptr | (*lptr != 0);
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} else {
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low = *lptr;
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*lptr = *hptr >> (count - 64);
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*lptr |= (*hptr << (128 - count)) != 0 || low != 0;
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}
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*hptr = 0;
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} else {
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low = *lptr;
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*lptr = low >> count | *hptr << (64 - count);
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*lptr |= (low << (64 - count)) != 0;
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*hptr = *hptr >> count;
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}
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}
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static union ieee754dp _dp_maddf(union ieee754dp z, union ieee754dp x,
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union ieee754dp y, enum maddf_flags flags)
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{
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int re;
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int rs;
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unsigned int lxm;
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unsigned int hxm;
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unsigned int lym;
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unsigned int hym;
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u64 lrm;
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u64 hrm;
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u64 lzm;
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u64 hzm;
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u64 t;
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u64 at;
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int s;
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COMPXDP;
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COMPYDP;
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COMPZDP;
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EXPLODEXDP;
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EXPLODEYDP;
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EXPLODEZDP;
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FLUSHXDP;
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FLUSHYDP;
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FLUSHZDP;
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ieee754_clearcx();
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/*
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* Handle the cases when at least one of x, y or z is a NaN.
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* Order of precedence is sNaN, qNaN and z, x, y.
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*/
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if (zc == IEEE754_CLASS_SNAN)
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return ieee754dp_nanxcpt(z);
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if (xc == IEEE754_CLASS_SNAN)
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return ieee754dp_nanxcpt(x);
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if (yc == IEEE754_CLASS_SNAN)
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return ieee754dp_nanxcpt(y);
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if (zc == IEEE754_CLASS_QNAN)
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return z;
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if (xc == IEEE754_CLASS_QNAN)
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return x;
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if (yc == IEEE754_CLASS_QNAN)
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return y;
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if (zc == IEEE754_CLASS_DNORM)
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DPDNORMZ;
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/* ZERO z cases are handled separately below */
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switch (CLPAIR(xc, yc)) {
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/*
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* Infinity handling
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*/
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_ZERO):
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_INF):
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ieee754_setcx(IEEE754_INVALID_OPERATION);
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return ieee754dp_indef();
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_INF):
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_INF):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_NORM):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_DNORM):
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case CLPAIR(IEEE754_CLASS_INF, IEEE754_CLASS_INF):
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if ((zc == IEEE754_CLASS_INF) &&
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((!(flags & MADDF_NEGATE_PRODUCT) && (zs != (xs ^ ys))) ||
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((flags & MADDF_NEGATE_PRODUCT) && (zs == (xs ^ ys))))) {
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/*
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* Cases of addition of infinities with opposite signs
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* or subtraction of infinities with same signs.
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*/
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ieee754_setcx(IEEE754_INVALID_OPERATION);
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return ieee754dp_indef();
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}
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/*
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* z is here either not an infinity, or an infinity having the
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* same sign as product (x*y) (in case of MADDF.D instruction)
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* or product -(x*y) (in MSUBF.D case). The result must be an
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* infinity, and its sign is determined only by the value of
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* (flags & MADDF_NEGATE_PRODUCT) and the signs of x and y.
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*/
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if (flags & MADDF_NEGATE_PRODUCT)
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return ieee754dp_inf(1 ^ (xs ^ ys));
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else
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return ieee754dp_inf(xs ^ ys);
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_ZERO):
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_NORM):
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case CLPAIR(IEEE754_CLASS_ZERO, IEEE754_CLASS_DNORM):
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_ZERO):
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_ZERO):
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if (zc == IEEE754_CLASS_INF)
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return ieee754dp_inf(zs);
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if (zc == IEEE754_CLASS_ZERO) {
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/* Handle cases +0 + (-0) and similar ones. */
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if ((!(flags & MADDF_NEGATE_PRODUCT)
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&& (zs == (xs ^ ys))) ||
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((flags & MADDF_NEGATE_PRODUCT)
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&& (zs != (xs ^ ys))))
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/*
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* Cases of addition of zeros of equal signs
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* or subtraction of zeroes of opposite signs.
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* The sign of the resulting zero is in any
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* such case determined only by the sign of z.
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*/
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return z;
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return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);
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}
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/* x*y is here 0, and z is not 0, so just return z */
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return z;
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_DNORM):
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DPDNORMX;
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/* fall through */
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_DNORM):
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if (zc == IEEE754_CLASS_INF)
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return ieee754dp_inf(zs);
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DPDNORMY;
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break;
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case CLPAIR(IEEE754_CLASS_DNORM, IEEE754_CLASS_NORM):
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if (zc == IEEE754_CLASS_INF)
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return ieee754dp_inf(zs);
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DPDNORMX;
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break;
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case CLPAIR(IEEE754_CLASS_NORM, IEEE754_CLASS_NORM):
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if (zc == IEEE754_CLASS_INF)
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return ieee754dp_inf(zs);
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/* continue to real computations */
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}
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/* Finally get to do some computation */
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/*
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* Do the multiplication bit first
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*
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* rm = xm * ym, re = xe + ye basically
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*
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* At this point xm and ym should have been normalized.
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*/
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assert(xm & DP_HIDDEN_BIT);
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assert(ym & DP_HIDDEN_BIT);
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re = xe + ye;
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rs = xs ^ ys;
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if (flags & MADDF_NEGATE_PRODUCT)
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rs ^= 1;
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/* shunt to top of word */
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xm <<= 64 - (DP_FBITS + 1);
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ym <<= 64 - (DP_FBITS + 1);
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/*
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* Multiply 64 bits xm and ym to give 128 bits result in hrm:lrm.
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*/
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lxm = xm;
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hxm = xm >> 32;
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lym = ym;
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hym = ym >> 32;
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lrm = DPXMULT(lxm, lym);
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hrm = DPXMULT(hxm, hym);
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t = DPXMULT(lxm, hym);
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at = lrm + (t << 32);
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hrm += at < lrm;
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lrm = at;
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hrm = hrm + (t >> 32);
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t = DPXMULT(hxm, lym);
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at = lrm + (t << 32);
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hrm += at < lrm;
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lrm = at;
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hrm = hrm + (t >> 32);
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/* Put explicit bit at bit 126 if necessary */
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if ((int64_t)hrm < 0) {
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lrm = (hrm << 63) | (lrm >> 1);
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hrm = hrm >> 1;
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re++;
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}
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assert(hrm & (1 << 62));
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if (zc == IEEE754_CLASS_ZERO) {
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/*
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* Move explicit bit from bit 126 to bit 55 since the
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* ieee754dp_format code expects the mantissa to be
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* 56 bits wide (53 + 3 rounding bits).
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*/
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srl128(&hrm, &lrm, (126 - 55));
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return ieee754dp_format(rs, re, lrm);
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}
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/* Move explicit bit from bit 52 to bit 126 */
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lzm = 0;
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hzm = zm << 10;
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assert(hzm & (1 << 62));
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/* Make the exponents the same */
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if (ze > re) {
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/*
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* Have to shift y fraction right to align.
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*/
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s = ze - re;
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srl128(&hrm, &lrm, s);
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re += s;
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} else if (re > ze) {
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/*
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* Have to shift x fraction right to align.
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*/
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s = re - ze;
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srl128(&hzm, &lzm, s);
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ze += s;
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}
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assert(ze == re);
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assert(ze <= DP_EMAX);
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/* Do the addition */
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if (zs == rs) {
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/*
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* Generate 128 bit result by adding two 127 bit numbers
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* leaving result in hzm:lzm, zs and ze.
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*/
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hzm = hzm + hrm + (lzm > (lzm + lrm));
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lzm = lzm + lrm;
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if ((int64_t)hzm < 0) { /* carry out */
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srl128(&hzm, &lzm, 1);
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ze++;
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}
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} else {
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if (hzm > hrm || (hzm == hrm && lzm >= lrm)) {
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hzm = hzm - hrm - (lzm < lrm);
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lzm = lzm - lrm;
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} else {
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hzm = hrm - hzm - (lrm < lzm);
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lzm = lrm - lzm;
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zs = rs;
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}
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if (lzm == 0 && hzm == 0)
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return ieee754dp_zero(ieee754_csr.rm == FPU_CSR_RD);
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/*
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* Put explicit bit at bit 126 if necessary.
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*/
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if (hzm == 0) {
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/* left shift by 63 or 64 bits */
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if ((int64_t)lzm < 0) {
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/* MSB of lzm is the explicit bit */
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hzm = lzm >> 1;
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lzm = lzm << 63;
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ze -= 63;
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} else {
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hzm = lzm;
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lzm = 0;
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ze -= 64;
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}
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}
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t = 0;
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while ((hzm >> (62 - t)) == 0)
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t++;
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assert(t <= 62);
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if (t) {
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hzm = hzm << t | lzm >> (64 - t);
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lzm = lzm << t;
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ze -= t;
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}
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}
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/*
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* Move explicit bit from bit 126 to bit 55 since the
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* ieee754dp_format code expects the mantissa to be
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* 56 bits wide (53 + 3 rounding bits).
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*/
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srl128(&hzm, &lzm, (126 - 55));
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return ieee754dp_format(zs, ze, lzm);
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}
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union ieee754dp ieee754dp_maddf(union ieee754dp z, union ieee754dp x,
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union ieee754dp y)
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{
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return _dp_maddf(z, x, y, 0);
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}
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union ieee754dp ieee754dp_msubf(union ieee754dp z, union ieee754dp x,
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union ieee754dp y)
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{
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return _dp_maddf(z, x, y, MADDF_NEGATE_PRODUCT);
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}
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