418 lines
10 KiB
C
418 lines
10 KiB
C
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/*
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* MediaTek display pulse-width-modulation controller driver.
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* Copyright (c) 2015 MediaTek Inc.
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* Author: YH Huang <yh.huang@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pwm.h>
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#include <linux/slab.h>
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#include <linux/of_address.h>
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#include <linux/delay.h>
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#define DISP_PWM_EN 0x00
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#define PWM_CLKDIV_SHIFT 16
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#define PWM_CLKDIV_MAX 0x3ff
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#define PWM_CLKDIV_MASK (PWM_CLKDIV_MAX << PWM_CLKDIV_SHIFT)
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#define PWM_PERIOD_BIT_WIDTH 12
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#define PWM_PERIOD_MASK ((1 << PWM_PERIOD_BIT_WIDTH) - 1)
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#define PWM_HIGH_WIDTH_SHIFT 16
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#define PWM_HIGH_WIDTH_MASK (0x1fff << PWM_HIGH_WIDTH_SHIFT)
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#undef pr_fmt
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#define pr_fmt(fmt) "[mtk_disp_pwm]" fmt
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struct mtk_pwm_data {
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u32 enable_mask;
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unsigned int con0;
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u32 con0_sel;
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unsigned int con1;
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bool has_commit;
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unsigned int commit;
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unsigned int commit_mask;
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unsigned int bls_debug;
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u32 bls_debug_mask;
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};
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struct mtk_disp_pwm {
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struct pwm_chip chip;
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const struct mtk_pwm_data *data;
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struct clk *clk_main;
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struct clk *clk_mm;
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void __iomem *base;
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void __iomem *pmw_src_addr;
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bool pwm_src_enabled;
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};
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static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip)
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{
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return container_of(chip, struct mtk_disp_pwm, chip);
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}
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static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset,
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u32 mask, u32 data)
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{
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void __iomem *address = mdp->base + offset;
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u32 value;
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value = readl(address);
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value &= ~mask;
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value |= data;
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writel(value, address);
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}
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static int get_pwm_src_base(struct device *dev, struct mtk_disp_pwm *mdp)
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{
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int ret = 0;
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struct device_node *node;
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void __iomem *pmw_src_base;
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u32 addr_offset = 0;
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node = of_parse_phandle(dev->of_node, "pwm_src_base", 0);
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if (!node) {
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dev_info(dev, "find pwm_src node failed\n");
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return -1;
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}
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pmw_src_base = of_iomap(node, 0);
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if (!pmw_src_base) {
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dev_info(dev, "find pwm_src address failed\n");
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of_node_put(node);
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return -1;
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}
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ret = of_property_read_u32(dev->of_node, "pwm_src_addr", &addr_offset);
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if (ret >= 0)
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mdp->pmw_src_addr = pmw_src_base + addr_offset;
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dev_info(dev, "get pwm_src_addr=%x\n", addr_offset);
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of_node_put(node);
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return ret;
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}
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static int pwm_src_power_on(struct mtk_disp_pwm *mdp)
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{
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u32 regosc;
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if (!mdp->pmw_src_addr || mdp->pwm_src_enabled)
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return 0;
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mdp->pwm_src_enabled = true;
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regosc = readl(mdp->pmw_src_addr);
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regosc = regosc | 0x1;
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writel(regosc, mdp->pmw_src_addr);
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udelay(150);
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regosc = readl(mdp->pmw_src_addr);
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regosc = regosc | 0x4;
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writel(regosc, mdp->pmw_src_addr);
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regosc = readl(mdp->pmw_src_addr);
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return 0;
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}
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static int pwm_src_power_off(struct mtk_disp_pwm *mdp)
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{
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u32 regosc;
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if (!mdp->pmw_src_addr || !mdp->pwm_src_enabled)
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return 0;
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mdp->pwm_src_enabled = false;
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regosc = readl(mdp->pmw_src_addr);
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regosc = regosc & (~0x4);
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writel(regosc, mdp->pmw_src_addr);
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udelay(150);
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regosc = readl(mdp->pmw_src_addr);
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regosc = regosc & (~0x1);
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writel(regosc, mdp->pmw_src_addr);
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regosc = readl(mdp->pmw_src_addr);
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return 0;
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}
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static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
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u32 clk_div, period, high_width, value;
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u64 div, rate;
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int err;
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/*
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* Find period, high_width and clk_div to suit duty_ns and period_ns.
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* Calculate proper div value to keep period value in the bound.
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*
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* period_ns = 10^9 * (clk_div + 1) * (period + 1) / PWM_CLK_RATE
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* duty_ns = 10^9 * (clk_div + 1) * high_width / PWM_CLK_RATE
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*
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* period = (PWM_CLK_RATE * period_ns) / (10^9 * (clk_div + 1)) - 1
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* high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1))
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*/
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dev_dbg(mdp->chip.dev, "duty=%d period=%d\n", duty_ns, period_ns);
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rate = clk_get_rate(mdp->clk_main);
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clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >>
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PWM_PERIOD_BIT_WIDTH;
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if (clk_div > PWM_CLKDIV_MAX)
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return -EINVAL;
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dev_dbg(mdp->chip.dev, "rate=%lld clk_div=%d\n", rate, clk_div);
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div = NSEC_PER_SEC * (clk_div + 1);
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period = div64_u64(rate * period_ns, div);
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if (period > 0)
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period--;
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high_width = div64_u64(rate * duty_ns, div);
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value = period | (high_width << PWM_HIGH_WIDTH_SHIFT);
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dev_dbg(mdp->chip.dev, "high_width=%d period=%d\n",
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high_width, period);
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pwm_src_power_on(mdp);
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err = clk_enable(mdp->clk_main);
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if (err < 0)
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return err;
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err = clk_enable(mdp->clk_mm);
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if (err < 0) {
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clk_disable(mdp->clk_main);
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return err;
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}
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mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
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PWM_CLKDIV_MASK,
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clk_div << PWM_CLKDIV_SHIFT);
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mtk_disp_pwm_update_bits(mdp, mdp->data->con1,
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PWM_PERIOD_MASK | PWM_HIGH_WIDTH_MASK,
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value);
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if (mdp->data->has_commit) {
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mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
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mdp->data->commit_mask,
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mdp->data->commit_mask);
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mtk_disp_pwm_update_bits(mdp, mdp->data->commit,
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mdp->data->commit_mask,
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0x0);
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}
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clk_disable(mdp->clk_mm);
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clk_disable(mdp->clk_main);
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return 0;
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}
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static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
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int err;
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dev_info(mdp->chip.dev, "%s\n", __func__);
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err = clk_enable(mdp->clk_main);
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if (err < 0)
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return err;
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err = clk_enable(mdp->clk_mm);
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if (err < 0) {
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clk_disable(mdp->clk_main);
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return err;
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}
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pwm_src_power_on(mdp);
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mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
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mdp->data->enable_mask);
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return 0;
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}
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static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip);
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dev_dbg(mdp->chip.dev, "%s\n", __func__);
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mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask,
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0x0);
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clk_disable(mdp->clk_mm);
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clk_disable(mdp->clk_main);
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pwm_src_power_off(mdp);
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}
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static const struct pwm_ops mtk_disp_pwm_ops = {
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.config = mtk_disp_pwm_config,
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.enable = mtk_disp_pwm_enable,
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.disable = mtk_disp_pwm_disable,
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.owner = THIS_MODULE,
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};
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static int mtk_disp_pwm_probe(struct platform_device *pdev)
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{
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struct mtk_disp_pwm *mdp;
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struct resource *r;
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struct clk *pwm_src;
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int ret;
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mdp = devm_kzalloc(&pdev->dev, sizeof(*mdp), GFP_KERNEL);
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if (!mdp)
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return -ENOMEM;
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mdp->data = of_device_get_match_data(&pdev->dev);
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mdp->base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(mdp->base))
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return PTR_ERR(mdp->base);
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mdp->clk_main = devm_clk_get(&pdev->dev, "main");
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if (IS_ERR(mdp->clk_main))
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return PTR_ERR(mdp->clk_main);
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mdp->clk_mm = devm_clk_get(&pdev->dev, "mm");
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if (IS_ERR(mdp->clk_mm))
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return PTR_ERR(mdp->clk_mm);
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ret = clk_prepare(mdp->clk_main);
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if (ret < 0)
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return ret;
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ret = clk_prepare(mdp->clk_mm);
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if (ret < 0)
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goto disable_clk_main;
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pwm_src = devm_clk_get(&pdev->dev, "pwm_src");
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if (!IS_ERR(pwm_src) && get_pwm_src_base(&pdev->dev, mdp) >= 0) {
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clk_enable(mdp->clk_mm);
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clk_set_parent(mdp->clk_mm, pwm_src);
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clk_disable(mdp->clk_mm);
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dev_info(&pdev->dev, "select clk_mm with pwm_src\n");
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}
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mdp->chip.dev = &pdev->dev;
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mdp->chip.ops = &mtk_disp_pwm_ops;
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mdp->chip.base = -1;
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mdp->chip.npwm = 1;
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ret = pwmchip_add(&mdp->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
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goto disable_clk_mm;
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}
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platform_set_drvdata(pdev, mdp);
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/*
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* For MT2701, disable double buffer before writing register
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* and select manual mode and use PWM_PERIOD/PWM_HIGH_WIDTH.
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*/
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if (!mdp->data->has_commit) {
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mtk_disp_pwm_update_bits(mdp, mdp->data->bls_debug,
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mdp->data->bls_debug_mask,
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mdp->data->bls_debug_mask);
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mtk_disp_pwm_update_bits(mdp, mdp->data->con0,
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mdp->data->con0_sel,
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mdp->data->con0_sel);
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}
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return 0;
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disable_clk_mm:
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clk_unprepare(mdp->clk_mm);
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disable_clk_main:
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clk_unprepare(mdp->clk_main);
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return ret;
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}
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static int mtk_disp_pwm_remove(struct platform_device *pdev)
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{
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struct mtk_disp_pwm *mdp = platform_get_drvdata(pdev);
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int ret;
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ret = pwmchip_remove(&mdp->chip);
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clk_unprepare(mdp->clk_mm);
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clk_unprepare(mdp->clk_main);
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return ret;
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}
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static const struct mtk_pwm_data mt2701_pwm_data = {
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.enable_mask = BIT(16),
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||
|
|
.con0 = 0xa8,
|
||
|
|
.con0_sel = 0x2,
|
||
|
|
.con1 = 0xac,
|
||
|
|
.has_commit = false,
|
||
|
|
.bls_debug = 0xb0,
|
||
|
|
.bls_debug_mask = 0x3,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct mtk_pwm_data mt8173_pwm_data = {
|
||
|
|
.enable_mask = BIT(0),
|
||
|
|
.con0 = 0x10,
|
||
|
|
.con0_sel = 0x0,
|
||
|
|
.con1 = 0x14,
|
||
|
|
.has_commit = true,
|
||
|
|
.commit = 0x8,
|
||
|
|
.commit_mask = 0x1,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct mtk_pwm_data mt6799_pwm_data = {
|
||
|
|
.enable_mask = BIT(0),
|
||
|
|
.con0 = 0x18,
|
||
|
|
.con0_sel = 0x0,
|
||
|
|
.con1 = 0x1C,
|
||
|
|
.has_commit = true,
|
||
|
|
.commit = 0xC,
|
||
|
|
.commit_mask = 0x1,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id mtk_disp_pwm_of_match[] = {
|
||
|
|
{.compatible = "mediatek,mt2701-disp-pwm", .data = &mt2701_pwm_data},
|
||
|
|
{.compatible = "mediatek,mt6595-disp-pwm", .data = &mt8173_pwm_data},
|
||
|
|
{.compatible = "mediatek,mt6779-disp-pwm", .data = &mt6799_pwm_data},
|
||
|
|
{.compatible = "mediatek,mt6873-disp-pwm", .data = &mt6799_pwm_data},
|
||
|
|
{.compatible = "mediatek,mt6885-disp-pwm", .data = &mt6799_pwm_data},
|
||
|
|
{.compatible = "mediatek,mt6853-disp-pwm", .data = &mt6799_pwm_data},
|
||
|
|
{.compatible = "mediatek,mt8173-disp-pwm", .data = &mt8173_pwm_data},
|
||
|
|
{.compatible = "mediatek,mt6833-disp-pwm", .data = &mt6799_pwm_data},
|
||
|
|
{.compatible = "mediatek,mt6877-disp-pwm", .data = &mt6799_pwm_data},
|
||
|
|
{.compatible = "mediatek,mt6781-disp-pwm", .data = &mt6799_pwm_data},
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, mtk_disp_pwm_of_match);
|
||
|
|
|
||
|
|
static struct platform_driver mtk_disp_pwm_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "mediatek-disp-pwm",
|
||
|
|
.of_match_table = mtk_disp_pwm_of_match,
|
||
|
|
},
|
||
|
|
.probe = mtk_disp_pwm_probe,
|
||
|
|
.remove = mtk_disp_pwm_remove,
|
||
|
|
};
|
||
|
|
module_platform_driver(mtk_disp_pwm_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("YH Huang <yh.huang@mediatek.com>");
|
||
|
|
MODULE_DESCRIPTION("MediaTek SoC display PWM driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|