344 lines
9.2 KiB
C
344 lines
9.2 KiB
C
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/*
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* CXL Flash Device Driver
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*
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* Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
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* Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
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*
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* Copyright (C) 2015 IBM Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _CXLFLASH_COMMON_H
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#define _CXLFLASH_COMMON_H
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#include <linux/async.h>
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#include <linux/cdev.h>
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#include <linux/irq_poll.h>
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#include <linux/list.h>
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#include <linux/rwsem.h>
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#include <linux/types.h>
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#include <scsi/scsi.h>
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#include <scsi/scsi_cmnd.h>
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#include <scsi/scsi_device.h>
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#include "backend.h"
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extern const struct file_operations cxlflash_cxl_fops;
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#define MAX_CONTEXT CXLFLASH_MAX_CONTEXT /* num contexts per afu */
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#define MAX_FC_PORTS CXLFLASH_MAX_FC_PORTS /* max ports per AFU */
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#define LEGACY_FC_PORTS 2 /* legacy ports per AFU */
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#define CHAN2PORTBANK(_x) ((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK))
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#define CHAN2BANKPORT(_x) ((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1))
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#define CHAN2PORTMASK(_x) (1 << (_x)) /* channel to port mask */
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#define PORTMASK2CHAN(_x) (ilog2((_x))) /* port mask to channel */
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#define PORTNUM2CHAN(_x) ((_x) - 1) /* port number to channel */
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#define CXLFLASH_BLOCK_SIZE 4096 /* 4K blocks */
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#define CXLFLASH_MAX_XFER_SIZE 16777216 /* 16MB transfer */
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#define CXLFLASH_MAX_SECTORS (CXLFLASH_MAX_XFER_SIZE/512) /* SCSI wants
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* max_sectors
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* in units of
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* 512 byte
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* sectors
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*/
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#define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))
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/* AFU command retry limit */
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#define MC_RETRY_CNT 5 /* Sufficient for SCSI and certain AFU errors */
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/* Command management definitions */
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#define CXLFLASH_MAX_CMDS 256
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#define CXLFLASH_MAX_CMDS_PER_LUN CXLFLASH_MAX_CMDS
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/* RRQ for master issued cmds */
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#define NUM_RRQ_ENTRY CXLFLASH_MAX_CMDS
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/* SQ for master issued cmds */
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#define NUM_SQ_ENTRY CXLFLASH_MAX_CMDS
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/* Hardware queue definitions */
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#define CXLFLASH_DEF_HWQS 1
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#define CXLFLASH_MAX_HWQS 8
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#define PRIMARY_HWQ 0
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static inline void check_sizes(void)
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{
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BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK);
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BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS);
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}
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/* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
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#define CMD_BUFSIZE SIZE_4K
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enum cxlflash_lr_state {
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LINK_RESET_INVALID,
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LINK_RESET_REQUIRED,
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LINK_RESET_COMPLETE
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};
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enum cxlflash_init_state {
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INIT_STATE_NONE,
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INIT_STATE_PCI,
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INIT_STATE_AFU,
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INIT_STATE_SCSI,
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INIT_STATE_CDEV
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};
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enum cxlflash_state {
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STATE_PROBING, /* Initial state during probe */
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STATE_PROBED, /* Temporary state, probe completed but EEH occurred */
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STATE_NORMAL, /* Normal running state, everything good */
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STATE_RESET, /* Reset state, trying to reset/recover */
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STATE_FAILTERM /* Failed/terminating state, error out users/threads */
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};
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enum cxlflash_hwq_mode {
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HWQ_MODE_RR, /* Roundrobin (default) */
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HWQ_MODE_TAG, /* Distribute based on block MQ tag */
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HWQ_MODE_CPU, /* CPU affinity */
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MAX_HWQ_MODE
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};
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/*
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* Each context has its own set of resource handles that is visible
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* only from that context.
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*/
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struct cxlflash_cfg {
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struct afu *afu;
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const struct cxlflash_backend_ops *ops;
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struct pci_dev *dev;
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struct pci_device_id *dev_id;
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struct Scsi_Host *host;
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int num_fc_ports;
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struct cdev cdev;
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struct device *chardev;
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ulong cxlflash_regs_pci;
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struct work_struct work_q;
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enum cxlflash_init_state init_state;
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enum cxlflash_lr_state lr_state;
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int lr_port;
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atomic_t scan_host_needed;
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void *afu_cookie;
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atomic_t recovery_threads;
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struct mutex ctx_recovery_mutex;
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struct mutex ctx_tbl_list_mutex;
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struct rw_semaphore ioctl_rwsem;
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struct ctx_info *ctx_tbl[MAX_CONTEXT];
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struct list_head ctx_err_recovery; /* contexts w/ recovery pending */
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struct file_operations cxl_fops;
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/* Parameters that are LUN table related */
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int last_lun_index[MAX_FC_PORTS];
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int promote_lun_index;
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struct list_head lluns; /* list of llun_info structs */
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wait_queue_head_t tmf_waitq;
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spinlock_t tmf_slock;
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bool tmf_active;
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bool ws_unmap; /* Write-same unmap supported */
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wait_queue_head_t reset_waitq;
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enum cxlflash_state state;
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async_cookie_t async_reset_cookie;
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};
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struct afu_cmd {
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struct sisl_ioarcb rcb; /* IOARCB (cache line aligned) */
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struct sisl_ioasa sa; /* IOASA must follow IOARCB */
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struct afu *parent;
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struct scsi_cmnd *scp;
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struct completion cevent;
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struct list_head queue;
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u32 hwq_index;
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u8 cmd_tmf:1,
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cmd_aborted:1;
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struct list_head list; /* Pending commands link */
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/* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
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* However for performance reasons the IOARCB/IOASA should be
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* cache line aligned.
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*/
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} __aligned(cache_line_size());
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static inline struct afu_cmd *sc_to_afuc(struct scsi_cmnd *sc)
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{
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return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd));
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}
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static inline struct afu_cmd *sc_to_afuci(struct scsi_cmnd *sc)
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{
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struct afu_cmd *afuc = sc_to_afuc(sc);
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INIT_LIST_HEAD(&afuc->queue);
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return afuc;
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}
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static inline struct afu_cmd *sc_to_afucz(struct scsi_cmnd *sc)
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{
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struct afu_cmd *afuc = sc_to_afuc(sc);
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memset(afuc, 0, sizeof(*afuc));
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return sc_to_afuci(sc);
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}
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struct hwq {
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/* Stuff requiring alignment go first. */
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struct sisl_ioarcb sq[NUM_SQ_ENTRY]; /* 16K SQ */
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u64 rrq_entry[NUM_RRQ_ENTRY]; /* 2K RRQ */
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/* Beware of alignment till here. Preferably introduce new
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* fields after this point
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*/
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struct afu *afu;
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void *ctx_cookie;
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struct sisl_host_map __iomem *host_map; /* MC host map */
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struct sisl_ctrl_map __iomem *ctrl_map; /* MC control map */
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ctx_hndl_t ctx_hndl; /* master's context handle */
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u32 index; /* Index of this hwq */
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int num_irqs; /* Number of interrupts requested for context */
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struct list_head pending_cmds; /* Commands pending completion */
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atomic_t hsq_credits;
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spinlock_t hsq_slock; /* Hardware send queue lock */
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struct sisl_ioarcb *hsq_start;
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struct sisl_ioarcb *hsq_end;
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struct sisl_ioarcb *hsq_curr;
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spinlock_t hrrq_slock;
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u64 *hrrq_start;
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u64 *hrrq_end;
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u64 *hrrq_curr;
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bool toggle;
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bool hrrq_online;
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s64 room;
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struct irq_poll irqpoll;
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} __aligned(cache_line_size());
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struct afu {
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struct hwq hwqs[CXLFLASH_MAX_HWQS];
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int (*send_cmd)(struct afu *afu, struct afu_cmd *cmd);
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int (*context_reset)(struct hwq *hwq);
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/* AFU HW */
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struct cxlflash_afu_map __iomem *afu_map; /* entire MMIO map */
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atomic_t cmds_active; /* Number of currently active AFU commands */
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struct mutex sync_active; /* Mutex to serialize AFU commands */
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u64 hb;
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u32 internal_lun; /* User-desired LUN mode for this AFU */
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u32 num_hwqs; /* Number of hardware queues */
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u32 desired_hwqs; /* Desired h/w queues, effective on AFU reset */
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enum cxlflash_hwq_mode hwq_mode; /* Steering mode for h/w queues */
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u32 hwq_rr_count; /* Count to distribute traffic for roundrobin */
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char version[16];
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u64 interface_version;
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u32 irqpoll_weight;
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struct cxlflash_cfg *parent; /* Pointer back to parent cxlflash_cfg */
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};
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static inline struct hwq *get_hwq(struct afu *afu, u32 index)
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{
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WARN_ON(index >= CXLFLASH_MAX_HWQS);
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return &afu->hwqs[index];
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}
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static inline bool afu_is_irqpoll_enabled(struct afu *afu)
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{
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return !!afu->irqpoll_weight;
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}
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static inline bool afu_has_cap(struct afu *afu, u64 cap)
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{
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u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT;
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return afu_cap & cap;
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}
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static inline bool afu_is_ocxl_lisn(struct afu *afu)
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{
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return afu_has_cap(afu, SISL_INTVER_CAP_OCXL_LISN);
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}
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static inline bool afu_is_afu_debug(struct afu *afu)
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{
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return afu_has_cap(afu, SISL_INTVER_CAP_AFU_DEBUG);
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}
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static inline bool afu_is_lun_provision(struct afu *afu)
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{
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return afu_has_cap(afu, SISL_INTVER_CAP_LUN_PROVISION);
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}
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static inline bool afu_is_sq_cmd_mode(struct afu *afu)
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{
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return afu_has_cap(afu, SISL_INTVER_CAP_SQ_CMD_MODE);
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}
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static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu)
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{
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return afu_has_cap(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE);
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}
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static inline u64 lun_to_lunid(u64 lun)
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{
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__be64 lun_id;
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int_to_scsilun(lun, (struct scsi_lun *)&lun_id);
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return be64_to_cpu(lun_id);
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}
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static inline struct fc_port_bank __iomem *get_fc_port_bank(
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struct cxlflash_cfg *cfg, int i)
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{
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struct afu *afu = cfg->afu;
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return &afu->afu_map->global.bank[CHAN2PORTBANK(i)];
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}
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static inline __be64 __iomem *get_fc_port_regs(struct cxlflash_cfg *cfg, int i)
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{
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struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
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return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0];
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}
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static inline __be64 __iomem *get_fc_port_luns(struct cxlflash_cfg *cfg, int i)
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{
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struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
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return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0];
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}
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int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode);
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void cxlflash_list_init(void);
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void cxlflash_term_global_luns(void);
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void cxlflash_free_errpage(void);
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int cxlflash_ioctl(struct scsi_device *sdev, int cmd, void __user *arg);
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void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg);
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int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg);
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void cxlflash_term_local_luns(struct cxlflash_cfg *cfg);
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void cxlflash_restore_luntable(struct cxlflash_cfg *cfg);
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#endif /* ifndef _CXLFLASH_COMMON_H */
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