520 lines
17 KiB
C
520 lines
17 KiB
C
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/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (C) 2003-2018 Cavium, Inc.
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/*
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* Functions for RGMII/GMII/MII initialization, configuration,
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* and monitoring.
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*/
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-config.h>
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#include <asm/octeon/cvmx-pko.h>
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#include <asm/octeon/cvmx-helper.h>
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#include <asm/octeon/cvmx-helper-board.h>
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#include <asm/octeon/cvmx-npi-defs.h>
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#include <asm/octeon/cvmx-gmxx-defs.h>
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#include <asm/octeon/cvmx-asxx-defs.h>
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#include <asm/octeon/cvmx-dbg-defs.h>
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/**
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* Probe RGMII ports and determine the number present
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*
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* @interface: Interface to probe
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*
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* Returns Number of RGMII/GMII/MII ports (0-4).
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*/
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int __cvmx_helper_rgmii_probe(int interface)
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{
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int num_ports = 0;
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union cvmx_gmxx_inf_mode mode;
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mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
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if (mode.s.type) {
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if (OCTEON_IS_MODEL(OCTEON_CN38XX)
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|| OCTEON_IS_MODEL(OCTEON_CN58XX)) {
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cvmx_dprintf("ERROR: RGMII initialize called in "
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"SPI interface\n");
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} else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
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|| OCTEON_IS_MODEL(OCTEON_CN30XX)
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|| OCTEON_IS_MODEL(OCTEON_CN50XX)) {
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/*
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* On these chips "type" says we're in
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* GMII/MII mode. This limits us to 2 ports
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*/
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num_ports = 2;
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} else {
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cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
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__func__);
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}
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} else {
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if (OCTEON_IS_MODEL(OCTEON_CN38XX)
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|| OCTEON_IS_MODEL(OCTEON_CN58XX)) {
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num_ports = 4;
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} else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
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|| OCTEON_IS_MODEL(OCTEON_CN30XX)
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|| OCTEON_IS_MODEL(OCTEON_CN50XX)) {
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num_ports = 3;
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} else {
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cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n",
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__func__);
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}
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}
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return num_ports;
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}
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/**
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* Put an RGMII interface in loopback mode. Internal packets sent
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* out will be received back again on the same port. Externally
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* received packets will echo back out.
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*
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* @port: IPD port number to loop.
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*/
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void cvmx_helper_rgmii_internal_loopback(int port)
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{
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int interface = (port >> 4) & 1;
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int index = port & 0xf;
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uint64_t tmp;
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union cvmx_gmxx_prtx_cfg gmx_cfg;
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gmx_cfg.u64 = 0;
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gmx_cfg.s.duplex = 1;
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gmx_cfg.s.slottime = 1;
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gmx_cfg.s.speed = 1;
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cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
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cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
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cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
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cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
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tmp = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
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cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp);
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tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface));
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cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp);
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tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface));
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cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp);
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gmx_cfg.s.en = 1;
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cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
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}
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/**
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* Workaround ASX setup errata with CN38XX pass1
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*
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* @interface: Interface to setup
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* @port: Port to setup (0..3)
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* @cpu_clock_hz:
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* Chip frequency in Hertz
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*
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* Returns Zero on success, negative on failure
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*/
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static int __cvmx_helper_errata_asx_pass1(int interface, int port,
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int cpu_clock_hz)
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{
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/* Set hi water mark as per errata GMX-4 */
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if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000)
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cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12);
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else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000)
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cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11);
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else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000)
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cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10);
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else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000)
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cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9);
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else
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cvmx_dprintf("Illegal clock frequency (%d). "
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"CVMX_ASXX_TX_HI_WATERX not set\n", cpu_clock_hz);
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return 0;
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}
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/**
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* Configure all of the ASX, GMX, and PKO registers required
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* to get RGMII to function on the supplied interface.
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*
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* @interface: PKO Interface to configure (0 or 1)
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*
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* Returns Zero on success
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*/
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int __cvmx_helper_rgmii_enable(int interface)
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{
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int num_ports = cvmx_helper_ports_on_interface(interface);
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int port;
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struct cvmx_sysinfo *sys_info_ptr = cvmx_sysinfo_get();
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union cvmx_gmxx_inf_mode mode;
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union cvmx_asxx_tx_prt_en asx_tx;
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union cvmx_asxx_rx_prt_en asx_rx;
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mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
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if (mode.s.en == 0)
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return -1;
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if ((OCTEON_IS_MODEL(OCTEON_CN38XX) ||
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OCTEON_IS_MODEL(OCTEON_CN58XX)) && mode.s.type == 1)
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/* Ignore SPI interfaces */
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return -1;
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/* Configure the ASX registers needed to use the RGMII ports */
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asx_tx.u64 = 0;
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asx_tx.s.prt_en = cvmx_build_mask(num_ports);
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cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64);
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asx_rx.u64 = 0;
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asx_rx.s.prt_en = cvmx_build_mask(num_ports);
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cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64);
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/* Configure the GMX registers needed to use the RGMII ports */
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for (port = 0; port < num_ports; port++) {
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/* Setting of CVMX_GMXX_TXX_THRESH has been moved to
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__cvmx_helper_setup_gmx() */
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if (cvmx_octeon_is_pass1())
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__cvmx_helper_errata_asx_pass1(interface, port,
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sys_info_ptr->
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cpu_clock_hz);
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else {
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/*
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* Configure more flexible RGMII preamble
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* checking. Pass 1 doesn't support this
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* feature.
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*/
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union cvmx_gmxx_rxx_frm_ctl frm_ctl;
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frm_ctl.u64 =
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cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL
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(port, interface));
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/* New field, so must be compile time */
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frm_ctl.s.pre_free = 1;
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cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface),
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frm_ctl.u64);
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}
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/*
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* Each pause frame transmitted will ask for about 10M
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* bit times before resume. If buffer space comes
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* available before that time has expired, an XON
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* pause frame (0 time) will be transmitted to restart
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* the flow.
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*/
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cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface),
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20000);
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cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL
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(port, interface), 19000);
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if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
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cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface),
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16);
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cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface),
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16);
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} else {
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cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface),
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24);
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cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface),
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24);
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}
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}
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__cvmx_helper_setup_gmx(interface, num_ports);
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/* enable the ports now */
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for (port = 0; port < num_ports; port++) {
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union cvmx_gmxx_prtx_cfg gmx_cfg;
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gmx_cfg.u64 =
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cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface));
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gmx_cfg.s.en = 1;
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cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface),
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gmx_cfg.u64);
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}
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__cvmx_interrupt_asxx_enable(interface);
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__cvmx_interrupt_gmxx_enable(interface);
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return 0;
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}
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/**
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* Return the link state of an IPD/PKO port as returned by
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* auto negotiation. The result of this function may not match
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* Octeon's link config if auto negotiation has changed since
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* the last call to cvmx_helper_link_set().
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*
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* @ipd_port: IPD/PKO port to query
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*
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* Returns Link state
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*/
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cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port)
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{
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int interface = cvmx_helper_get_interface_num(ipd_port);
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int index = cvmx_helper_get_interface_index_num(ipd_port);
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union cvmx_asxx_prt_loop asxx_prt_loop;
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asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
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if (asxx_prt_loop.s.int_loop & (1 << index)) {
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/* Force 1Gbps full duplex on internal loopback */
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cvmx_helper_link_info_t result;
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result.u64 = 0;
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result.s.full_duplex = 1;
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result.s.link_up = 1;
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result.s.speed = 1000;
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return result;
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} else
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return __cvmx_helper_board_link_get(ipd_port);
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}
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/**
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* Configure an IPD/PKO port for the specified link state. This
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* function does not influence auto negotiation at the PHY level.
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* The passed link state must always match the link state returned
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* by cvmx_helper_link_get().
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*
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* @ipd_port: IPD/PKO port to configure
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* @link_info: The new link state
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*
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* Returns Zero on success, negative on failure
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*/
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int __cvmx_helper_rgmii_link_set(int ipd_port,
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cvmx_helper_link_info_t link_info)
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{
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int result = 0;
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int interface = cvmx_helper_get_interface_num(ipd_port);
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int index = cvmx_helper_get_interface_index_num(ipd_port);
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union cvmx_gmxx_prtx_cfg original_gmx_cfg;
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union cvmx_gmxx_prtx_cfg new_gmx_cfg;
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union cvmx_pko_mem_queue_qos pko_mem_queue_qos;
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union cvmx_pko_mem_queue_qos pko_mem_queue_qos_save[16];
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union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp;
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union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp_save;
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int i;
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/* Ignore speed sets in the simulator */
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if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
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return 0;
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/* Read the current settings so we know the current enable state */
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original_gmx_cfg.u64 =
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cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
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new_gmx_cfg = original_gmx_cfg;
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/* Disable the lowest level RX */
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cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
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cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) &
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~(1 << index));
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memset(pko_mem_queue_qos_save, 0, sizeof(pko_mem_queue_qos_save));
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/* Disable all queues so that TX should become idle */
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for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) {
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int queue = cvmx_pko_get_base_queue(ipd_port) + i;
|
||
|
|
cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);
|
||
|
|
pko_mem_queue_qos.u64 = cvmx_read_csr(CVMX_PKO_MEM_QUEUE_QOS);
|
||
|
|
pko_mem_queue_qos.s.pid = ipd_port;
|
||
|
|
pko_mem_queue_qos.s.qid = queue;
|
||
|
|
pko_mem_queue_qos_save[i] = pko_mem_queue_qos;
|
||
|
|
pko_mem_queue_qos.s.qos_mask = 0;
|
||
|
|
cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos.u64);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Disable backpressure */
|
||
|
|
gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
|
||
|
|
gmx_tx_ovr_bp_save = gmx_tx_ovr_bp;
|
||
|
|
gmx_tx_ovr_bp.s.bp &= ~(1 << index);
|
||
|
|
gmx_tx_ovr_bp.s.en |= 1 << index;
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64);
|
||
|
|
cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface));
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Poll the GMX state machine waiting for it to become
|
||
|
|
* idle. Preferably we should only change speed when it is
|
||
|
|
* idle. If it doesn't become idle we will still do the speed
|
||
|
|
* change, but there is a slight chance that GMX will
|
||
|
|
* lockup.
|
||
|
|
*/
|
||
|
|
cvmx_write_csr(CVMX_NPI_DBG_SELECT,
|
||
|
|
interface * 0x800 + index * 0x100 + 0x880);
|
||
|
|
CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 7,
|
||
|
|
==, 0, 10000);
|
||
|
|
CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 0xf,
|
||
|
|
==, 0, 10000);
|
||
|
|
|
||
|
|
/* Disable the port before we make any changes */
|
||
|
|
new_gmx_cfg.s.en = 0;
|
||
|
|
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
|
||
|
|
cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
|
||
|
|
|
||
|
|
/* Set full/half duplex */
|
||
|
|
if (cvmx_octeon_is_pass1())
|
||
|
|
/* Half duplex is broken for 38XX Pass 1 */
|
||
|
|
new_gmx_cfg.s.duplex = 1;
|
||
|
|
else if (!link_info.s.link_up)
|
||
|
|
/* Force full duplex on down links */
|
||
|
|
new_gmx_cfg.s.duplex = 1;
|
||
|
|
else
|
||
|
|
new_gmx_cfg.s.duplex = link_info.s.full_duplex;
|
||
|
|
|
||
|
|
/* Set the link speed. Anything unknown is set to 1Gbps */
|
||
|
|
if (link_info.s.speed == 10) {
|
||
|
|
new_gmx_cfg.s.slottime = 0;
|
||
|
|
new_gmx_cfg.s.speed = 0;
|
||
|
|
} else if (link_info.s.speed == 100) {
|
||
|
|
new_gmx_cfg.s.slottime = 0;
|
||
|
|
new_gmx_cfg.s.speed = 0;
|
||
|
|
} else {
|
||
|
|
new_gmx_cfg.s.slottime = 1;
|
||
|
|
new_gmx_cfg.s.speed = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Adjust the clocks */
|
||
|
|
if (link_info.s.speed == 10) {
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 50);
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
|
||
|
|
} else if (link_info.s.speed == 100) {
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 5);
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40);
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0);
|
||
|
|
} else {
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
|
||
|
|
if ((link_info.s.speed == 10) || (link_info.s.speed == 100)) {
|
||
|
|
union cvmx_gmxx_inf_mode mode;
|
||
|
|
mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface));
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Port .en .type .p0mii Configuration
|
||
|
|
* ---- --- ----- ------ -----------------------------------------
|
||
|
|
* X 0 X X All links are disabled.
|
||
|
|
* 0 1 X 0 Port 0 is RGMII
|
||
|
|
* 0 1 X 1 Port 0 is MII
|
||
|
|
* 1 1 0 X Ports 1 and 2 are configured as RGMII ports.
|
||
|
|
* 1 1 1 X Port 1: GMII/MII; Port 2: disabled. GMII or
|
||
|
|
* MII port is selected by GMX_PRT1_CFG[SPEED].
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* In MII mode, CLK_CNT = 1. */
|
||
|
|
if (((index == 0) && (mode.s.p0mii == 1))
|
||
|
|
|| ((index != 0) && (mode.s.type == 1))) {
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TXX_CLK
|
||
|
|
(index, interface), 1);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Do a read to make sure all setup stuff is complete */
|
||
|
|
cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
|
||
|
|
|
||
|
|
/* Save the new GMX setting without enabling the port */
|
||
|
|
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
|
||
|
|
|
||
|
|
/* Enable the lowest level RX */
|
||
|
|
cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
|
||
|
|
cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) | (1 <<
|
||
|
|
index));
|
||
|
|
|
||
|
|
/* Re-enable the TX path */
|
||
|
|
for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) {
|
||
|
|
int queue = cvmx_pko_get_base_queue(ipd_port) + i;
|
||
|
|
cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue);
|
||
|
|
cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS,
|
||
|
|
pko_mem_queue_qos_save[i].u64);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Restore backpressure */
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp_save.u64);
|
||
|
|
|
||
|
|
/* Restore the GMX enable state. Port config is complete */
|
||
|
|
new_gmx_cfg.s.en = original_gmx_cfg.s.en;
|
||
|
|
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64);
|
||
|
|
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* Configure a port for internal and/or external loopback. Internal loopback
|
||
|
|
* causes packets sent by the port to be received by Octeon. External loopback
|
||
|
|
* causes packets received from the wire to sent out again.
|
||
|
|
*
|
||
|
|
* @ipd_port: IPD/PKO port to loopback.
|
||
|
|
* @enable_internal:
|
||
|
|
* Non zero if you want internal loopback
|
||
|
|
* @enable_external:
|
||
|
|
* Non zero if you want external loopback
|
||
|
|
*
|
||
|
|
* Returns Zero on success, negative on failure.
|
||
|
|
*/
|
||
|
|
int __cvmx_helper_rgmii_configure_loopback(int ipd_port, int enable_internal,
|
||
|
|
int enable_external)
|
||
|
|
{
|
||
|
|
int interface = cvmx_helper_get_interface_num(ipd_port);
|
||
|
|
int index = cvmx_helper_get_interface_index_num(ipd_port);
|
||
|
|
int original_enable;
|
||
|
|
union cvmx_gmxx_prtx_cfg gmx_cfg;
|
||
|
|
union cvmx_asxx_prt_loop asxx_prt_loop;
|
||
|
|
|
||
|
|
/* Read the current enable state and save it */
|
||
|
|
gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
|
||
|
|
original_enable = gmx_cfg.s.en;
|
||
|
|
/* Force port to be disabled */
|
||
|
|
gmx_cfg.s.en = 0;
|
||
|
|
if (enable_internal) {
|
||
|
|
/* Force speed if we're doing internal loopback */
|
||
|
|
gmx_cfg.s.duplex = 1;
|
||
|
|
gmx_cfg.s.slottime = 1;
|
||
|
|
gmx_cfg.s.speed = 1;
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1);
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200);
|
||
|
|
cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000);
|
||
|
|
}
|
||
|
|
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
|
||
|
|
|
||
|
|
/* Set the loopback bits */
|
||
|
|
asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface));
|
||
|
|
if (enable_internal)
|
||
|
|
asxx_prt_loop.s.int_loop |= 1 << index;
|
||
|
|
else
|
||
|
|
asxx_prt_loop.s.int_loop &= ~(1 << index);
|
||
|
|
if (enable_external)
|
||
|
|
asxx_prt_loop.s.ext_loop |= 1 << index;
|
||
|
|
else
|
||
|
|
asxx_prt_loop.s.ext_loop &= ~(1 << index);
|
||
|
|
cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), asxx_prt_loop.u64);
|
||
|
|
|
||
|
|
/* Force enables in internal loopback */
|
||
|
|
if (enable_internal) {
|
||
|
|
uint64_t tmp;
|
||
|
|
tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface));
|
||
|
|
cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface),
|
||
|
|
(1 << index) | tmp);
|
||
|
|
tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface));
|
||
|
|
cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface),
|
||
|
|
(1 << index) | tmp);
|
||
|
|
original_enable = 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Restore the enable state */
|
||
|
|
gmx_cfg.s.en = original_enable;
|
||
|
|
cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64);
|
||
|
|
return 0;
|
||
|
|
}
|