134 lines
3 KiB
C
134 lines
3 KiB
C
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/*
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* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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*/
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#include <linux/clk-provider.h>
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#include <linux/clkdev.h>
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#include <linux/clk/at91_pmc.h>
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#include <linux/of.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "pmc.h"
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#define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw)
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struct clk_plldiv {
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struct clk_hw hw;
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struct regmap *regmap;
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};
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static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_plldiv *plldiv = to_clk_plldiv(hw);
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unsigned int mckr;
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regmap_read(plldiv->regmap, AT91_PMC_MCKR, &mckr);
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if (mckr & AT91_PMC_PLLADIV2)
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return parent_rate / 2;
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return parent_rate;
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}
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static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *parent_rate)
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{
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unsigned long div;
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if (rate > *parent_rate)
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return *parent_rate;
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div = *parent_rate / 2;
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if (rate < div)
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return div;
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if (rate - div < *parent_rate - rate)
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return div;
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return *parent_rate;
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}
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static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_plldiv *plldiv = to_clk_plldiv(hw);
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if ((parent_rate != rate) && (parent_rate / 2 != rate))
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return -EINVAL;
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regmap_update_bits(plldiv->regmap, AT91_PMC_MCKR, AT91_PMC_PLLADIV2,
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parent_rate != rate ? AT91_PMC_PLLADIV2 : 0);
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return 0;
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}
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static const struct clk_ops plldiv_ops = {
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.recalc_rate = clk_plldiv_recalc_rate,
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.round_rate = clk_plldiv_round_rate,
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.set_rate = clk_plldiv_set_rate,
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};
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static struct clk_hw * __init
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at91_clk_register_plldiv(struct regmap *regmap, const char *name,
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const char *parent_name)
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{
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struct clk_plldiv *plldiv;
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struct clk_hw *hw;
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struct clk_init_data init = {};
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int ret;
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plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL);
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if (!plldiv)
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return ERR_PTR(-ENOMEM);
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init.name = name;
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init.ops = &plldiv_ops;
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init.parent_names = parent_name ? &parent_name : NULL;
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init.num_parents = parent_name ? 1 : 0;
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init.flags = CLK_SET_RATE_GATE;
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plldiv->hw.init = &init;
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plldiv->regmap = regmap;
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hw = &plldiv->hw;
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ret = clk_hw_register(NULL, &plldiv->hw);
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if (ret) {
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kfree(plldiv);
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hw = ERR_PTR(ret);
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}
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return hw;
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}
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static void __init
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of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
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{
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struct clk_hw *hw;
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const char *parent_name;
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const char *name = np->name;
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struct regmap *regmap;
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parent_name = of_clk_get_parent_name(np, 0);
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of_property_read_string(np, "clock-output-names", &name);
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regmap = syscon_node_to_regmap(of_get_parent(np));
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if (IS_ERR(regmap))
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return;
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hw = at91_clk_register_plldiv(regmap, name, parent_name);
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if (IS_ERR(hw))
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return;
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of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw);
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}
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CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
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of_at91sam9x5_clk_plldiv_setup);
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