344 lines
8.5 KiB
C
344 lines
8.5 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright (c) 2019 MediaTek Inc.
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#include <linux/interrupt.h>
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#include <linux/mfd/mt6357/core.h>
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#include <linux/mfd/mt6357/registers.h>
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#include <linux/mfd/mt6358/core.h>
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#include <linux/mfd/mt6358/registers.h>
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#include <linux/mfd/mt6359/core.h>
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#include <linux/mfd/mt6359/registers.h>
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#include <linux/mfd/mt6397/core.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/wakeup_reason.h>
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#define DEBUG_PMIC_IRQ 1
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struct irq_top_t {
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int hwirq_base;
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unsigned int num_int_regs;
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unsigned int en_reg;
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unsigned int en_reg_shift;
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unsigned int sta_reg;
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unsigned int sta_reg_shift;
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unsigned int top_offset;
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};
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#if DEBUG_PMIC_IRQ
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struct irq_name_t {
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const char *name;
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};
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static struct irq_name_t mt6357_irq_name[] = MT6357_IRQ_NAME_GEN();
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static struct irq_name_t mt6358_irq_name[] = MT6358_IRQ_NAME_GEN();
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static struct irq_name_t mt6359_irq_name[] = MT6359_IRQ_NAME_GEN();
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#endif
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struct pmic_irq_data {
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unsigned int num_top;
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unsigned int num_pmic_irqs;
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unsigned int reg_width;
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unsigned short top_int_status_reg;
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bool *enable_hwirq;
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bool *cache_hwirq;
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struct irq_top_t *pmic_ints;
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#if DEBUG_PMIC_IRQ
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struct irq_name_t *irq_name;
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#endif
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};
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static struct irq_top_t mt6357_ints[] = {
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MT6357_TOP_GEN(BUCK),
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MT6357_TOP_GEN(LDO),
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MT6357_TOP_GEN(PSC),
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MT6357_TOP_GEN(SCK),
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MT6357_TOP_GEN(BM),
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MT6357_TOP_GEN(HK),
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MT6357_TOP_GEN(AUD),
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MT6357_TOP_GEN(MISC),
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};
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static struct irq_top_t mt6358_ints[] = {
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MT6358_TOP_GEN(BUCK),
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MT6358_TOP_GEN(LDO),
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MT6358_TOP_GEN(PSC),
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MT6358_TOP_GEN(SCK),
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MT6358_TOP_GEN(BM),
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MT6358_TOP_GEN(HK),
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MT6358_TOP_GEN(AUD),
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MT6358_TOP_GEN(MISC),
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};
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static struct irq_top_t mt6359_ints[] = {
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MT6359_TOP_GEN(BUCK),
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MT6359_TOP_GEN(LDO),
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MT6359_TOP_GEN(PSC),
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MT6359_TOP_GEN(SCK),
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MT6359_TOP_GEN(BM),
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MT6359_TOP_GEN(HK),
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MT6359_TOP_GEN(AUD),
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MT6359_TOP_GEN(MISC),
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};
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static void pmic_irq_enable(struct irq_data *data)
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{
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unsigned int hwirq = irqd_to_hwirq(data);
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struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
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struct pmic_irq_data *irqd = chip->irq_data;
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irqd->enable_hwirq[hwirq] = true;
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}
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static void pmic_irq_disable(struct irq_data *data)
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{
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unsigned int hwirq = irqd_to_hwirq(data);
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struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
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struct pmic_irq_data *irqd = chip->irq_data;
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irqd->enable_hwirq[hwirq] = false;
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}
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static void pmic_irq_lock(struct irq_data *data)
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{
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struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
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mutex_lock(&chip->irqlock);
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}
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static void pmic_irq_sync_unlock(struct irq_data *data)
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{
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unsigned int i, top_gp, en_reg, int_regs, shift;
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struct mt6397_chip *chip = irq_data_get_irq_chip_data(data);
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struct pmic_irq_data *irqd = chip->irq_data;
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for (i = 0; i < irqd->num_pmic_irqs; i++) {
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if (irqd->enable_hwirq[i] == irqd->cache_hwirq[i])
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continue;
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top_gp = 0;
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while ((top_gp + 1) < irqd->num_top &&
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i >= irqd->pmic_ints[top_gp + 1].hwirq_base)
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top_gp++;
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if (top_gp >= irqd->num_top) {
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mutex_unlock(&chip->irqlock);
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dev_err(chip->dev,
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"Failed to get top_group: %d\n", top_gp);
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return;
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}
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int_regs = (i - irqd->pmic_ints[top_gp].hwirq_base) /
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irqd->reg_width;
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en_reg = irqd->pmic_ints[top_gp].en_reg +
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irqd->pmic_ints[top_gp].en_reg_shift * int_regs;
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shift = (i - irqd->pmic_ints[top_gp].hwirq_base) %
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irqd->reg_width;
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regmap_update_bits(chip->regmap, en_reg, BIT(shift),
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irqd->enable_hwirq[i] << shift);
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irqd->cache_hwirq[i] = irqd->enable_hwirq[i];
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}
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mutex_unlock(&chip->irqlock);
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}
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static struct irq_chip mt6358_irq_chip = {
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.name = "mt6358-irq",
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.flags = IRQCHIP_SKIP_SET_WAKE,
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.irq_enable = pmic_irq_enable,
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.irq_disable = pmic_irq_disable,
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.irq_bus_lock = pmic_irq_lock,
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.irq_bus_sync_unlock = pmic_irq_sync_unlock,
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};
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static void mt6358_irq_sp_handler(struct mt6397_chip *chip,
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unsigned int top_gp)
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{
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unsigned int sta_reg, irq_status = 0;
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unsigned int hwirq, virq;
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int ret, i, j;
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struct pmic_irq_data *irqd = chip->irq_data;
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for (i = 0; i < irqd->pmic_ints[top_gp].num_int_regs; i++) {
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sta_reg = irqd->pmic_ints[top_gp].sta_reg +
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irqd->pmic_ints[top_gp].sta_reg_shift * i;
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ret = regmap_read(chip->regmap, sta_reg, &irq_status);
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if (ret) {
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dev_err(chip->dev,
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"Failed to read irq status: %d\n", ret);
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return;
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}
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if (!irq_status)
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continue;
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for (j = 0; j < irqd->reg_width ; j++) {
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if ((irq_status & BIT(j)) == 0)
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continue;
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hwirq = irqd->pmic_ints[top_gp].hwirq_base +
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irqd->reg_width * i + j;
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virq = irq_find_mapping(chip->irq_domain, hwirq);
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#if DEBUG_PMIC_IRQ
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dev_info(chip->dev,
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"Reg[0x%x]=0x%x,name=%s,hwirq=%d,type=%d\n",
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sta_reg, irq_status,
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irqd->irq_name[hwirq], hwirq,
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irq_get_trigger_type(virq));
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if (!strncmp(irqd->irq_name[hwirq].name, "chrdet_edge", 11)) {
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regmap_write(chip->regmap, sta_reg, BIT(j));
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irq_status &= ~BIT(j);
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}
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log_threaded_irq_wakeup_reason(virq, chip->irq);
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#endif
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#ifdef CONFIG_SEC_PM
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log_threaded_irq_wakeup_reason(virq, chip->irq);
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#endif /* CONFIG_SEC_PM */
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if (virq)
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handle_nested_irq(virq);
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}
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regmap_write(chip->regmap, sta_reg, irq_status);
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}
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}
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static irqreturn_t mt6358_irq_handler(int irq, void *data)
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{
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struct mt6397_chip *chip = data;
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struct pmic_irq_data *irqd = chip->irq_data;
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unsigned int top_irq_status = 0;
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unsigned int i = 0;
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int ret = 0;
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pm_stay_awake(chip->dev);
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ret = regmap_read(chip->regmap,
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irqd->top_int_status_reg,
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&top_irq_status);
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if (ret) {
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pm_relax(chip->dev);
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dev_err(chip->dev, "Can't read TOP_INT_STATUS ret=%d\n", ret);
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return IRQ_NONE;
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}
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for (i = 0; i < irqd->num_top; i++) {
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if (top_irq_status & BIT(irqd->pmic_ints[i].top_offset))
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mt6358_irq_sp_handler(chip, i);
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}
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pm_relax(chip->dev);
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return IRQ_HANDLED;
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}
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static int pmic_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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struct mt6397_chip *mt6397 = d->host_data;
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irq_set_chip_data(irq, mt6397);
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irq_set_chip_and_handler(irq, &mt6358_irq_chip, handle_level_irq);
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irq_set_nested_thread(irq, 1);
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irq_set_noprobe(irq);
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return 0;
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}
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static const struct irq_domain_ops mt6358_irq_domain_ops = {
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.map = pmic_irq_domain_map,
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.xlate = irq_domain_xlate_twocell,
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};
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int mt6358_irq_init(struct mt6397_chip *chip)
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{
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int i, j, ret;
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struct pmic_irq_data *irqd;
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irqd = devm_kzalloc(chip->dev, sizeof(*irqd), GFP_KERNEL);
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if (!irqd)
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return -ENOMEM;
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chip->irq_data = irqd;
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mutex_init(&chip->irqlock);
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switch (chip->chip_id) {
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case MT6357_CHIP_ID:
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irqd->num_top = ARRAY_SIZE(mt6357_ints);
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irqd->num_pmic_irqs = MT6357_IRQ_NR;
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irqd->reg_width = MT6357_REG_WIDTH;
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irqd->top_int_status_reg = MT6357_TOP_INT_STATUS0;
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irqd->pmic_ints = mt6357_ints;
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#if DEBUG_PMIC_IRQ
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irqd->irq_name = mt6357_irq_name;
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#endif
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break;
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case MT6358_CHIP_ID:
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irqd->num_top = ARRAY_SIZE(mt6358_ints);
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irqd->num_pmic_irqs = MT6358_IRQ_NR;
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irqd->reg_width = MT6358_REG_WIDTH;
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irqd->top_int_status_reg = MT6358_TOP_INT_STATUS0;
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irqd->pmic_ints = mt6358_ints;
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#if DEBUG_PMIC_IRQ
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irqd->irq_name = mt6358_irq_name;
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#endif
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break;
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case MT6359_CHIP_ID:
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irqd->num_top = ARRAY_SIZE(mt6359_ints);
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irqd->num_pmic_irqs = MT6359_IRQ_NR;
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irqd->reg_width = MT6359_REG_WIDTH;
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irqd->top_int_status_reg = MT6359_TOP_INT_STATUS0;
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irqd->pmic_ints = mt6359_ints;
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#if DEBUG_PMIC_IRQ
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irqd->irq_name = mt6359_irq_name;
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#endif
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break;
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default:
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dev_err(chip->dev, "unsupported chip: 0x%x\n", chip->chip_id);
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ret = -ENODEV;
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break;
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}
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irqd->enable_hwirq = devm_kcalloc(chip->dev,
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irqd->num_pmic_irqs,
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sizeof(bool),
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GFP_KERNEL);
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if (!irqd->enable_hwirq)
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return -ENOMEM;
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irqd->cache_hwirq = devm_kcalloc(chip->dev,
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irqd->num_pmic_irqs,
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sizeof(bool),
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GFP_KERNEL);
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if (!irqd->cache_hwirq)
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return -ENOMEM;
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/* Disable all interrupt for initializing */
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for (i = 0; i < irqd->num_top; i++) {
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for (j = 0; j < irqd->pmic_ints[i].num_int_regs; j++)
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regmap_write(chip->regmap,
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irqd->pmic_ints[i].en_reg +
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irqd->pmic_ints[i].en_reg_shift * j, 0);
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}
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chip->irq_domain = irq_domain_add_linear(chip->dev->of_node,
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irqd->num_pmic_irqs,
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&mt6358_irq_domain_ops, chip);
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if (!chip->irq_domain) {
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dev_err(chip->dev, "could not create irq domain\n");
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return -ENODEV;
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}
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ret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,
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mt6358_irq_handler,
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IRQF_ONESHOT,
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mt6358_irq_chip.name, chip);
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if (ret) {
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dev_err(chip->dev, "failed to register irq=%d; err: %d\n",
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chip->irq, ret);
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return ret;
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}
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enable_irq_wake(chip->irq);
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return ret;
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}
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