451 lines
11 KiB
C
451 lines
11 KiB
C
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/*
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* ASoC driver for Cirrus Logic EP93xx AC97 controller.
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*
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* Copyright (c) 2010 Mika Westerberg
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*
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* Based on s3c-ac97 ASoC driver by Jaswinder Singh.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <sound/core.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/ac97_codec.h>
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#include <sound/soc.h>
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#include <linux/platform_data/dma-ep93xx.h>
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#include "ep93xx-pcm.h"
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/*
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* Per channel (1-4) registers.
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*/
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#define AC97CH(n) (((n) - 1) * 0x20)
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#define AC97DR(n) (AC97CH(n) + 0x0000)
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#define AC97RXCR(n) (AC97CH(n) + 0x0004)
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#define AC97RXCR_REN BIT(0)
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#define AC97RXCR_RX3 BIT(3)
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#define AC97RXCR_RX4 BIT(4)
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#define AC97RXCR_CM BIT(15)
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#define AC97TXCR(n) (AC97CH(n) + 0x0008)
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#define AC97TXCR_TEN BIT(0)
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#define AC97TXCR_TX3 BIT(3)
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#define AC97TXCR_TX4 BIT(4)
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#define AC97TXCR_CM BIT(15)
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#define AC97SR(n) (AC97CH(n) + 0x000c)
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#define AC97SR_TXFE BIT(1)
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#define AC97SR_TXUE BIT(6)
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#define AC97RISR(n) (AC97CH(n) + 0x0010)
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#define AC97ISR(n) (AC97CH(n) + 0x0014)
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#define AC97IE(n) (AC97CH(n) + 0x0018)
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/*
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* Global AC97 controller registers.
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*/
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#define AC97S1DATA 0x0080
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#define AC97S2DATA 0x0084
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#define AC97S12DATA 0x0088
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#define AC97RGIS 0x008c
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#define AC97GIS 0x0090
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#define AC97IM 0x0094
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/*
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* Common bits for RGIS, GIS and IM registers.
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*/
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#define AC97_SLOT2RXVALID BIT(1)
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#define AC97_CODECREADY BIT(5)
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#define AC97_SLOT2TXCOMPLETE BIT(6)
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#define AC97EOI 0x0098
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#define AC97EOI_WINT BIT(0)
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#define AC97EOI_CODECREADY BIT(1)
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#define AC97GCR 0x009c
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#define AC97GCR_AC97IFE BIT(0)
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#define AC97RESET 0x00a0
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#define AC97RESET_TIMEDRESET BIT(0)
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#define AC97SYNC 0x00a4
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#define AC97SYNC_TIMEDSYNC BIT(0)
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#define AC97_TIMEOUT msecs_to_jiffies(5)
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/**
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* struct ep93xx_ac97_info - EP93xx AC97 controller info structure
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* @lock: mutex serializing access to the bus (slot 1 & 2 ops)
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* @dev: pointer to the platform device dev structure
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* @regs: mapped AC97 controller registers
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* @done: bus ops wait here for an interrupt
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*/
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struct ep93xx_ac97_info {
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struct mutex lock;
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struct device *dev;
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void __iomem *regs;
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struct completion done;
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struct snd_dmaengine_dai_dma_data dma_params_rx;
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struct snd_dmaengine_dai_dma_data dma_params_tx;
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};
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/* currently ALSA only supports a single AC97 device */
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static struct ep93xx_ac97_info *ep93xx_ac97_info;
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static struct ep93xx_dma_data ep93xx_ac97_pcm_out = {
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.name = "ac97-pcm-out",
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.port = EP93XX_DMA_AAC1,
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.direction = DMA_MEM_TO_DEV,
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};
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static struct ep93xx_dma_data ep93xx_ac97_pcm_in = {
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.name = "ac97-pcm-in",
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.port = EP93XX_DMA_AAC1,
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.direction = DMA_DEV_TO_MEM,
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};
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static inline unsigned ep93xx_ac97_read_reg(struct ep93xx_ac97_info *info,
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unsigned reg)
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{
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return __raw_readl(info->regs + reg);
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}
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static inline void ep93xx_ac97_write_reg(struct ep93xx_ac97_info *info,
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unsigned reg, unsigned val)
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{
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__raw_writel(val, info->regs + reg);
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}
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static unsigned short ep93xx_ac97_read(struct snd_ac97 *ac97,
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unsigned short reg)
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{
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struct ep93xx_ac97_info *info = ep93xx_ac97_info;
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unsigned short val;
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mutex_lock(&info->lock);
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ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
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ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2RXVALID);
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if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT)) {
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dev_warn(info->dev, "timeout reading register %x\n", reg);
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mutex_unlock(&info->lock);
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return -ETIMEDOUT;
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}
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val = (unsigned short)ep93xx_ac97_read_reg(info, AC97S2DATA);
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mutex_unlock(&info->lock);
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return val;
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}
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static void ep93xx_ac97_write(struct snd_ac97 *ac97,
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unsigned short reg,
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unsigned short val)
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{
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struct ep93xx_ac97_info *info = ep93xx_ac97_info;
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mutex_lock(&info->lock);
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/*
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* Writes to the codec need to be done so that slot 2 is filled in
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* before slot 1.
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*/
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ep93xx_ac97_write_reg(info, AC97S2DATA, val);
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ep93xx_ac97_write_reg(info, AC97S1DATA, reg);
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ep93xx_ac97_write_reg(info, AC97IM, AC97_SLOT2TXCOMPLETE);
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if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
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dev_warn(info->dev, "timeout writing register %x\n", reg);
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mutex_unlock(&info->lock);
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}
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static void ep93xx_ac97_warm_reset(struct snd_ac97 *ac97)
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{
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struct ep93xx_ac97_info *info = ep93xx_ac97_info;
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mutex_lock(&info->lock);
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/*
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* We are assuming that before this functions gets called, the codec
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* BIT_CLK is stopped by forcing the codec into powerdown mode. We can
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* control the SYNC signal directly via AC97SYNC register. Using
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* TIMEDSYNC the controller will keep the SYNC high > 1us.
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*/
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ep93xx_ac97_write_reg(info, AC97SYNC, AC97SYNC_TIMEDSYNC);
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ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
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if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
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dev_warn(info->dev, "codec warm reset timeout\n");
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mutex_unlock(&info->lock);
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}
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static void ep93xx_ac97_cold_reset(struct snd_ac97 *ac97)
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{
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struct ep93xx_ac97_info *info = ep93xx_ac97_info;
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mutex_lock(&info->lock);
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/*
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* For doing cold reset, we disable the AC97 controller interface, clear
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* WINT and CODECREADY bits, and finally enable the interface again.
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*/
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ep93xx_ac97_write_reg(info, AC97GCR, 0);
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ep93xx_ac97_write_reg(info, AC97EOI, AC97EOI_CODECREADY | AC97EOI_WINT);
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ep93xx_ac97_write_reg(info, AC97GCR, AC97GCR_AC97IFE);
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/*
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* Now, assert the reset and wait for the codec to become ready.
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*/
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ep93xx_ac97_write_reg(info, AC97RESET, AC97RESET_TIMEDRESET);
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ep93xx_ac97_write_reg(info, AC97IM, AC97_CODECREADY);
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if (!wait_for_completion_timeout(&info->done, AC97_TIMEOUT))
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dev_warn(info->dev, "codec cold reset timeout\n");
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/*
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* Give the codec some time to come fully out from the reset. This way
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* we ensure that the subsequent reads/writes will work.
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*/
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usleep_range(15000, 20000);
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mutex_unlock(&info->lock);
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}
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static irqreturn_t ep93xx_ac97_interrupt(int irq, void *dev_id)
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{
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struct ep93xx_ac97_info *info = dev_id;
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unsigned status, mask;
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/*
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* Just mask out the interrupt and wake up the waiting thread.
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* Interrupts are cleared via reading/writing to slot 1 & 2 registers by
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* the waiting thread.
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*/
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status = ep93xx_ac97_read_reg(info, AC97GIS);
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mask = ep93xx_ac97_read_reg(info, AC97IM);
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mask &= ~status;
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ep93xx_ac97_write_reg(info, AC97IM, mask);
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complete(&info->done);
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return IRQ_HANDLED;
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}
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static struct snd_ac97_bus_ops ep93xx_ac97_ops = {
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.read = ep93xx_ac97_read,
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.write = ep93xx_ac97_write,
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.reset = ep93xx_ac97_cold_reset,
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.warm_reset = ep93xx_ac97_warm_reset,
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};
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static int ep93xx_ac97_trigger(struct snd_pcm_substream *substream,
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int cmd, struct snd_soc_dai *dai)
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{
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struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
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unsigned v = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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/*
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* Enable compact mode, TX slots 3 & 4, and the TX FIFO
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* itself.
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*/
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v |= AC97TXCR_CM;
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v |= AC97TXCR_TX3 | AC97TXCR_TX4;
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v |= AC97TXCR_TEN;
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ep93xx_ac97_write_reg(info, AC97TXCR(1), v);
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} else {
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/*
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* Enable compact mode, RX slots 3 & 4, and the RX FIFO
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* itself.
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*/
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v |= AC97RXCR_CM;
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v |= AC97RXCR_RX3 | AC97RXCR_RX4;
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v |= AC97RXCR_REN;
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ep93xx_ac97_write_reg(info, AC97RXCR(1), v);
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}
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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/*
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* As per Cirrus EP93xx errata described below:
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*
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* http://www.cirrus.com/en/pubs/errata/ER667E2B.pdf
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*
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* we will wait for the TX FIFO to be empty before
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* clearing the TEN bit.
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*/
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unsigned long timeout = jiffies + AC97_TIMEOUT;
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do {
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v = ep93xx_ac97_read_reg(info, AC97SR(1));
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if (time_after(jiffies, timeout)) {
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dev_warn(info->dev, "TX timeout\n");
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break;
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}
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} while (!(v & (AC97SR_TXFE | AC97SR_TXUE)));
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/* disable the TX FIFO */
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ep93xx_ac97_write_reg(info, AC97TXCR(1), 0);
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} else {
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/* disable the RX FIFO */
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ep93xx_ac97_write_reg(info, AC97RXCR(1), 0);
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}
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break;
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default:
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dev_warn(info->dev, "unknown command %d\n", cmd);
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return -EINVAL;
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}
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return 0;
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}
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static int ep93xx_ac97_dai_probe(struct snd_soc_dai *dai)
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{
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struct ep93xx_ac97_info *info = snd_soc_dai_get_drvdata(dai);
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info->dma_params_tx.filter_data = &ep93xx_ac97_pcm_out;
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info->dma_params_rx.filter_data = &ep93xx_ac97_pcm_in;
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dai->playback_dma_data = &info->dma_params_tx;
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dai->capture_dma_data = &info->dma_params_rx;
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return 0;
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}
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static const struct snd_soc_dai_ops ep93xx_ac97_dai_ops = {
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.trigger = ep93xx_ac97_trigger,
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};
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static struct snd_soc_dai_driver ep93xx_ac97_dai = {
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.name = "ep93xx-ac97",
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.id = 0,
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.bus_control = true,
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.probe = ep93xx_ac97_dai_probe,
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.playback = {
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.stream_name = "AC97 Playback",
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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.capture = {
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.stream_name = "AC97 Capture",
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.channels_min = 2,
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.channels_max = 2,
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.rates = SNDRV_PCM_RATE_8000_48000,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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},
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||
|
|
.ops = &ep93xx_ac97_dai_ops,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct snd_soc_component_driver ep93xx_ac97_component = {
|
||
|
|
.name = "ep93xx-ac97",
|
||
|
|
};
|
||
|
|
|
||
|
|
static int ep93xx_ac97_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct ep93xx_ac97_info *info;
|
||
|
|
struct resource *res;
|
||
|
|
int irq;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
|
||
|
|
if (!info)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||
|
|
info->regs = devm_ioremap_resource(&pdev->dev, res);
|
||
|
|
if (IS_ERR(info->regs))
|
||
|
|
return PTR_ERR(info->regs);
|
||
|
|
|
||
|
|
irq = platform_get_irq(pdev, 0);
|
||
|
|
if (irq <= 0)
|
||
|
|
return irq < 0 ? irq : -ENODEV;
|
||
|
|
|
||
|
|
ret = devm_request_irq(&pdev->dev, irq, ep93xx_ac97_interrupt,
|
||
|
|
IRQF_TRIGGER_HIGH, pdev->name, info);
|
||
|
|
if (ret)
|
||
|
|
goto fail;
|
||
|
|
|
||
|
|
dev_set_drvdata(&pdev->dev, info);
|
||
|
|
|
||
|
|
mutex_init(&info->lock);
|
||
|
|
init_completion(&info->done);
|
||
|
|
info->dev = &pdev->dev;
|
||
|
|
|
||
|
|
ep93xx_ac97_info = info;
|
||
|
|
platform_set_drvdata(pdev, info);
|
||
|
|
|
||
|
|
ret = snd_soc_set_ac97_ops(&ep93xx_ac97_ops);
|
||
|
|
if (ret)
|
||
|
|
goto fail;
|
||
|
|
|
||
|
|
ret = snd_soc_register_component(&pdev->dev, &ep93xx_ac97_component,
|
||
|
|
&ep93xx_ac97_dai, 1);
|
||
|
|
if (ret)
|
||
|
|
goto fail;
|
||
|
|
|
||
|
|
ret = devm_ep93xx_pcm_platform_register(&pdev->dev);
|
||
|
|
if (ret)
|
||
|
|
goto fail_unregister;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
fail_unregister:
|
||
|
|
snd_soc_unregister_component(&pdev->dev);
|
||
|
|
fail:
|
||
|
|
ep93xx_ac97_info = NULL;
|
||
|
|
snd_soc_set_ac97_ops(NULL);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int ep93xx_ac97_remove(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct ep93xx_ac97_info *info = platform_get_drvdata(pdev);
|
||
|
|
|
||
|
|
snd_soc_unregister_component(&pdev->dev);
|
||
|
|
|
||
|
|
/* disable the AC97 controller */
|
||
|
|
ep93xx_ac97_write_reg(info, AC97GCR, 0);
|
||
|
|
|
||
|
|
ep93xx_ac97_info = NULL;
|
||
|
|
|
||
|
|
snd_soc_set_ac97_ops(NULL);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_driver ep93xx_ac97_driver = {
|
||
|
|
.probe = ep93xx_ac97_probe,
|
||
|
|
.remove = ep93xx_ac97_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "ep93xx-ac97",
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
module_platform_driver(ep93xx_ac97_driver);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("EP93xx AC97 ASoC Driver");
|
||
|
|
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@iki.fi>");
|
||
|
|
MODULE_LICENSE("GPL");
|
||
|
|
MODULE_ALIAS("platform:ep93xx-ac97");
|