277 lines
7.9 KiB
C
277 lines
7.9 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
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#include <crypto/ctr.h>
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#include "cc_driver.h"
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#include "cc_ivgen.h"
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#include "cc_request_mgr.h"
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#include "cc_sram_mgr.h"
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#include "cc_buffer_mgr.h"
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/* The max. size of pool *MUST* be <= SRAM total size */
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#define CC_IVPOOL_SIZE 1024
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/* The first 32B fraction of pool are dedicated to the
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* next encryption "key" & "IV" for pool regeneration
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*/
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#define CC_IVPOOL_META_SIZE (CC_AES_IV_SIZE + AES_KEYSIZE_128)
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#define CC_IVPOOL_GEN_SEQ_LEN 4
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/**
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* struct cc_ivgen_ctx -IV pool generation context
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* @pool: the start address of the iv-pool resides in internal RAM
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* @ctr_key_dma: address of pool's encryption key material in internal RAM
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* @ctr_iv_dma: address of pool's counter iv in internal RAM
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* @next_iv_ofs: the offset to the next available IV in pool
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* @pool_meta: virt. address of the initial enc. key/IV
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* @pool_meta_dma: phys. address of the initial enc. key/IV
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*/
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struct cc_ivgen_ctx {
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cc_sram_addr_t pool;
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cc_sram_addr_t ctr_key;
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cc_sram_addr_t ctr_iv;
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u32 next_iv_ofs;
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u8 *pool_meta;
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dma_addr_t pool_meta_dma;
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};
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/*!
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* Generates CC_IVPOOL_SIZE of random bytes by
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* encrypting 0's using AES128-CTR.
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*
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* \param ivgen iv-pool context
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* \param iv_seq IN/OUT array to the descriptors sequence
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* \param iv_seq_len IN/OUT pointer to the sequence length
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*/
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static int cc_gen_iv_pool(struct cc_ivgen_ctx *ivgen_ctx,
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struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len)
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{
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unsigned int idx = *iv_seq_len;
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if ((*iv_seq_len + CC_IVPOOL_GEN_SEQ_LEN) > CC_IVPOOL_SEQ_LEN) {
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/* The sequence will be longer than allowed */
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return -EINVAL;
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}
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/* Setup key */
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hw_desc_init(&iv_seq[idx]);
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set_din_sram(&iv_seq[idx], ivgen_ctx->ctr_key, AES_KEYSIZE_128);
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set_setup_mode(&iv_seq[idx], SETUP_LOAD_KEY0);
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set_cipher_config0(&iv_seq[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
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set_flow_mode(&iv_seq[idx], S_DIN_to_AES);
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set_key_size_aes(&iv_seq[idx], CC_AES_128_BIT_KEY_SIZE);
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set_cipher_mode(&iv_seq[idx], DRV_CIPHER_CTR);
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idx++;
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/* Setup cipher state */
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hw_desc_init(&iv_seq[idx]);
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set_din_sram(&iv_seq[idx], ivgen_ctx->ctr_iv, CC_AES_IV_SIZE);
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set_cipher_config0(&iv_seq[idx], DESC_DIRECTION_ENCRYPT_ENCRYPT);
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set_flow_mode(&iv_seq[idx], S_DIN_to_AES);
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set_setup_mode(&iv_seq[idx], SETUP_LOAD_STATE1);
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set_key_size_aes(&iv_seq[idx], CC_AES_128_BIT_KEY_SIZE);
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set_cipher_mode(&iv_seq[idx], DRV_CIPHER_CTR);
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idx++;
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/* Perform dummy encrypt to skip first block */
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hw_desc_init(&iv_seq[idx]);
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set_din_const(&iv_seq[idx], 0, CC_AES_IV_SIZE);
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set_dout_sram(&iv_seq[idx], ivgen_ctx->pool, CC_AES_IV_SIZE);
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set_flow_mode(&iv_seq[idx], DIN_AES_DOUT);
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idx++;
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/* Generate IV pool */
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hw_desc_init(&iv_seq[idx]);
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set_din_const(&iv_seq[idx], 0, CC_IVPOOL_SIZE);
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set_dout_sram(&iv_seq[idx], ivgen_ctx->pool, CC_IVPOOL_SIZE);
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set_flow_mode(&iv_seq[idx], DIN_AES_DOUT);
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idx++;
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*iv_seq_len = idx; /* Update sequence length */
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/* queue ordering assures pool readiness */
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ivgen_ctx->next_iv_ofs = CC_IVPOOL_META_SIZE;
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return 0;
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}
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/*!
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* Generates the initial pool in SRAM.
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* This function should be invoked when resuming driver.
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*
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* \param drvdata
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*
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* \return int Zero for success, negative value otherwise.
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*/
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int cc_init_iv_sram(struct cc_drvdata *drvdata)
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{
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struct cc_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle;
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struct cc_hw_desc iv_seq[CC_IVPOOL_SEQ_LEN];
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unsigned int iv_seq_len = 0;
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int rc;
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/* Generate initial enc. key/iv */
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get_random_bytes(ivgen_ctx->pool_meta, CC_IVPOOL_META_SIZE);
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/* The first 32B reserved for the enc. Key/IV */
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ivgen_ctx->ctr_key = ivgen_ctx->pool;
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ivgen_ctx->ctr_iv = ivgen_ctx->pool + AES_KEYSIZE_128;
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/* Copy initial enc. key and IV to SRAM at a single descriptor */
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hw_desc_init(&iv_seq[iv_seq_len]);
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set_din_type(&iv_seq[iv_seq_len], DMA_DLLI, ivgen_ctx->pool_meta_dma,
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CC_IVPOOL_META_SIZE, NS_BIT);
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set_dout_sram(&iv_seq[iv_seq_len], ivgen_ctx->pool,
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CC_IVPOOL_META_SIZE);
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set_flow_mode(&iv_seq[iv_seq_len], BYPASS);
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iv_seq_len++;
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/* Generate initial pool */
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rc = cc_gen_iv_pool(ivgen_ctx, iv_seq, &iv_seq_len);
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if (rc)
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return rc;
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/* Fire-and-forget */
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return send_request_init(drvdata, iv_seq, iv_seq_len);
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}
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/*!
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* Free iv-pool and ivgen context.
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*
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* \param drvdata
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*/
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void cc_ivgen_fini(struct cc_drvdata *drvdata)
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{
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struct cc_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle;
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struct device *device = &drvdata->plat_dev->dev;
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if (!ivgen_ctx)
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return;
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if (ivgen_ctx->pool_meta) {
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memset(ivgen_ctx->pool_meta, 0, CC_IVPOOL_META_SIZE);
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dma_free_coherent(device, CC_IVPOOL_META_SIZE,
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ivgen_ctx->pool_meta,
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ivgen_ctx->pool_meta_dma);
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}
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ivgen_ctx->pool = NULL_SRAM_ADDR;
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}
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/*!
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* Allocates iv-pool and maps resources.
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* This function generates the first IV pool.
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*
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* \param drvdata Driver's private context
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*
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* \return int Zero for success, negative value otherwise.
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*/
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int cc_ivgen_init(struct cc_drvdata *drvdata)
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{
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struct cc_ivgen_ctx *ivgen_ctx;
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struct device *device = &drvdata->plat_dev->dev;
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int rc;
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/* Allocate "this" context */
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ivgen_ctx = devm_kzalloc(device, sizeof(*ivgen_ctx), GFP_KERNEL);
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if (!ivgen_ctx)
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return -ENOMEM;
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drvdata->ivgen_handle = ivgen_ctx;
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/* Allocate pool's header for initial enc. key/IV */
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ivgen_ctx->pool_meta = dma_alloc_coherent(device, CC_IVPOOL_META_SIZE,
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&ivgen_ctx->pool_meta_dma,
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GFP_KERNEL);
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if (!ivgen_ctx->pool_meta) {
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dev_err(device, "Not enough memory to allocate DMA of pool_meta (%u B)\n",
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CC_IVPOOL_META_SIZE);
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rc = -ENOMEM;
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goto out;
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}
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/* Allocate IV pool in SRAM */
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ivgen_ctx->pool = cc_sram_alloc(drvdata, CC_IVPOOL_SIZE);
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if (ivgen_ctx->pool == NULL_SRAM_ADDR) {
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dev_err(device, "SRAM pool exhausted\n");
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rc = -ENOMEM;
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goto out;
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}
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return cc_init_iv_sram(drvdata);
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out:
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cc_ivgen_fini(drvdata);
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return rc;
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}
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/*!
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* Acquires 16 Bytes IV from the iv-pool
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*
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* \param drvdata Driver private context
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* \param iv_out_dma Array of physical IV out addresses
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* \param iv_out_dma_len Length of iv_out_dma array (additional elements
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* of iv_out_dma array are ignore)
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* \param iv_out_size May be 8 or 16 bytes long
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* \param iv_seq IN/OUT array to the descriptors sequence
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* \param iv_seq_len IN/OUT pointer to the sequence length
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*
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* \return int Zero for success, negative value otherwise.
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*/
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int cc_get_iv(struct cc_drvdata *drvdata, dma_addr_t iv_out_dma[],
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unsigned int iv_out_dma_len, unsigned int iv_out_size,
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struct cc_hw_desc iv_seq[], unsigned int *iv_seq_len)
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{
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struct cc_ivgen_ctx *ivgen_ctx = drvdata->ivgen_handle;
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unsigned int idx = *iv_seq_len;
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struct device *dev = drvdata_to_dev(drvdata);
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unsigned int t;
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if (iv_out_size != CC_AES_IV_SIZE &&
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iv_out_size != CTR_RFC3686_IV_SIZE) {
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return -EINVAL;
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}
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if ((iv_out_dma_len + 1) > CC_IVPOOL_SEQ_LEN) {
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/* The sequence will be longer than allowed */
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return -EINVAL;
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}
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/* check that number of generated IV is limited to max dma address
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* iv buffer size
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*/
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if (iv_out_dma_len > CC_MAX_IVGEN_DMA_ADDRESSES) {
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/* The sequence will be longer than allowed */
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return -EINVAL;
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}
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for (t = 0; t < iv_out_dma_len; t++) {
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/* Acquire IV from pool */
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hw_desc_init(&iv_seq[idx]);
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set_din_sram(&iv_seq[idx], (ivgen_ctx->pool +
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ivgen_ctx->next_iv_ofs),
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iv_out_size);
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set_dout_dlli(&iv_seq[idx], iv_out_dma[t], iv_out_size,
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NS_BIT, 0);
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set_flow_mode(&iv_seq[idx], BYPASS);
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idx++;
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}
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/* Bypass operation is proceeded by crypto sequence, hence must
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* assure bypass-write-transaction by a memory barrier
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*/
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hw_desc_init(&iv_seq[idx]);
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set_din_no_dma(&iv_seq[idx], 0, 0xfffff0);
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set_dout_no_dma(&iv_seq[idx], 0, 0, 1);
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idx++;
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*iv_seq_len = idx; /* update seq length */
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/* Update iv index */
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ivgen_ctx->next_iv_ofs += iv_out_size;
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if ((CC_IVPOOL_SIZE - ivgen_ctx->next_iv_ofs) < CC_AES_IV_SIZE) {
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dev_dbg(dev, "Pool exhausted, regenerating iv-pool\n");
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/* pool is drained -regenerate it! */
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return cc_gen_iv_pool(ivgen_ctx, iv_seq, iv_seq_len);
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}
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return 0;
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}
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