394 lines
11 KiB
C
394 lines
11 KiB
C
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <drm/drmP.h>
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#include <drm/amdgpu_drm.h>
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#ifdef CONFIG_X86
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#include <asm/set_memory.h>
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#endif
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#include "amdgpu.h"
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/*
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* GART
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* The GART (Graphics Aperture Remapping Table) is an aperture
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* in the GPU's address space. System pages can be mapped into
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* the aperture and look like contiguous pages from the GPU's
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* perspective. A page table maps the pages in the aperture
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* to the actual backing pages in system memory.
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*
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* Radeon GPUs support both an internal GART, as described above,
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* and AGP. AGP works similarly, but the GART table is configured
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* and maintained by the northbridge rather than the driver.
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* Radeon hw has a separate AGP aperture that is programmed to
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* point to the AGP aperture provided by the northbridge and the
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* requests are passed through to the northbridge aperture.
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* Both AGP and internal GART can be used at the same time, however
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* that is not currently supported by the driver.
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*
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* This file handles the common internal GART management.
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*/
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/*
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* Common GART table functions.
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*/
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/**
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* amdgpu_dummy_page_init - init dummy page used by the driver
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate the dummy page used by the driver (all asics).
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* This dummy page is used by the driver as a filler for gart entries
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* when pages are taken out of the GART
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* Returns 0 on sucess, -ENOMEM on failure.
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*/
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static int amdgpu_gart_dummy_page_init(struct amdgpu_device *adev)
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{
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struct page *dummy_page = adev->mman.bdev.glob->dummy_read_page;
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if (adev->dummy_page_addr)
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return 0;
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adev->dummy_page_addr = pci_map_page(adev->pdev, dummy_page, 0,
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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if (pci_dma_mapping_error(adev->pdev, adev->dummy_page_addr)) {
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dev_err(&adev->pdev->dev, "Failed to DMA MAP the dummy page\n");
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adev->dummy_page_addr = 0;
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return -ENOMEM;
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}
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return 0;
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}
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/**
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* amdgpu_dummy_page_fini - free dummy page used by the driver
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*
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* @adev: amdgpu_device pointer
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*
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* Frees the dummy page used by the driver (all asics).
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*/
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static void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev)
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{
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if (!adev->dummy_page_addr)
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return;
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pci_unmap_page(adev->pdev, adev->dummy_page_addr,
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PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
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adev->dummy_page_addr = 0;
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}
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/**
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* amdgpu_gart_table_vram_alloc - allocate vram for gart page table
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate video memory for GART page table
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* (pcie r4xx, r5xx+). These asics require the
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* gart table to be in video memory.
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* Returns 0 for success, error for failure.
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*/
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int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
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{
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int r;
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if (adev->gart.robj == NULL) {
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struct amdgpu_bo_param bp;
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memset(&bp, 0, sizeof(bp));
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bp.size = adev->gart.table_size;
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bp.byte_align = PAGE_SIZE;
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bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
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bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
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AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
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bp.type = ttm_bo_type_kernel;
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bp.resv = NULL;
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r = amdgpu_bo_create(adev, &bp, &adev->gart.robj);
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if (r) {
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return r;
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}
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}
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return 0;
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}
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/**
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* amdgpu_gart_table_vram_pin - pin gart page table in vram
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*
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* @adev: amdgpu_device pointer
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*
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* Pin the GART page table in vram so it will not be moved
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* by the memory manager (pcie r4xx, r5xx+). These asics require the
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* gart table to be in video memory.
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* Returns 0 for success, error for failure.
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*/
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int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
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{
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int r;
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r = amdgpu_bo_reserve(adev->gart.robj, false);
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if (unlikely(r != 0))
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return r;
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r = amdgpu_bo_pin(adev->gart.robj, AMDGPU_GEM_DOMAIN_VRAM);
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if (r) {
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amdgpu_bo_unreserve(adev->gart.robj);
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return r;
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}
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r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
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if (r)
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amdgpu_bo_unpin(adev->gart.robj);
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amdgpu_bo_unreserve(adev->gart.robj);
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adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.robj);
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return r;
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}
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/**
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* amdgpu_gart_table_vram_unpin - unpin gart page table in vram
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*
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* @adev: amdgpu_device pointer
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*
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* Unpin the GART page table in vram (pcie r4xx, r5xx+).
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* These asics require the gart table to be in video memory.
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*/
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void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
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{
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int r;
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if (adev->gart.robj == NULL) {
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return;
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}
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r = amdgpu_bo_reserve(adev->gart.robj, true);
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if (likely(r == 0)) {
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amdgpu_bo_kunmap(adev->gart.robj);
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amdgpu_bo_unpin(adev->gart.robj);
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amdgpu_bo_unreserve(adev->gart.robj);
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adev->gart.ptr = NULL;
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}
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}
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/**
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* amdgpu_gart_table_vram_free - free gart page table vram
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*
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* @adev: amdgpu_device pointer
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*
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* Free the video memory used for the GART page table
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* (pcie r4xx, r5xx+). These asics require the gart table to
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* be in video memory.
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*/
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void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
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{
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if (adev->gart.robj == NULL) {
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return;
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}
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amdgpu_bo_unref(&adev->gart.robj);
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}
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/*
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* Common gart functions.
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*/
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/**
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* amdgpu_gart_unbind - unbind pages from the gart page table
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*
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* @adev: amdgpu_device pointer
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* @offset: offset into the GPU's gart aperture
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* @pages: number of pages to unbind
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*
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* Unbinds the requested pages from the gart page table and
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* replaces them with the dummy page (all asics).
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* Returns 0 for success, -EINVAL for failure.
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*/
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int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset,
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int pages)
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{
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unsigned t;
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unsigned p;
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int i, j;
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u64 page_base;
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/* Starting from VEGA10, system bit must be 0 to mean invalid. */
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uint64_t flags = 0;
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if (!adev->gart.ready) {
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WARN(1, "trying to unbind memory from uninitialized GART !\n");
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return -EINVAL;
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}
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t = offset / AMDGPU_GPU_PAGE_SIZE;
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p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
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for (i = 0; i < pages; i++, p++) {
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#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
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adev->gart.pages[p] = NULL;
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#endif
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page_base = adev->dummy_page_addr;
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if (!adev->gart.ptr)
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continue;
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for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
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amdgpu_gmc_set_pte_pde(adev, adev->gart.ptr,
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t, page_base, flags);
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page_base += AMDGPU_GPU_PAGE_SIZE;
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}
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}
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mb();
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amdgpu_asic_flush_hdp(adev, NULL);
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amdgpu_gmc_flush_gpu_tlb(adev, 0);
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return 0;
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}
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/**
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* amdgpu_gart_map - map dma_addresses into GART entries
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*
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* @adev: amdgpu_device pointer
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* @offset: offset into the GPU's gart aperture
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* @pages: number of pages to bind
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* @dma_addr: DMA addresses of pages
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*
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* Map the dma_addresses into GART entries (all asics).
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* Returns 0 for success, -EINVAL for failure.
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*/
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int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset,
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int pages, dma_addr_t *dma_addr, uint64_t flags,
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void *dst)
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{
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uint64_t page_base;
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unsigned i, j, t;
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if (!adev->gart.ready) {
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WARN(1, "trying to bind memory to uninitialized GART !\n");
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return -EINVAL;
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}
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t = offset / AMDGPU_GPU_PAGE_SIZE;
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for (i = 0; i < pages; i++) {
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page_base = dma_addr[i];
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for (j = 0; j < AMDGPU_GPU_PAGES_IN_CPU_PAGE; j++, t++) {
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amdgpu_gmc_set_pte_pde(adev, dst, t, page_base, flags);
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page_base += AMDGPU_GPU_PAGE_SIZE;
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}
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}
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return 0;
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}
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/**
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* amdgpu_gart_bind - bind pages into the gart page table
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*
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* @adev: amdgpu_device pointer
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* @offset: offset into the GPU's gart aperture
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* @pages: number of pages to bind
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* @pagelist: pages to bind
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* @dma_addr: DMA addresses of pages
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*
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* Binds the requested pages to the gart page table
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* (all asics).
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* Returns 0 for success, -EINVAL for failure.
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*/
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int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset,
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int pages, struct page **pagelist, dma_addr_t *dma_addr,
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uint64_t flags)
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{
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#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
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unsigned i,t,p;
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#endif
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int r;
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if (!adev->gart.ready) {
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WARN(1, "trying to bind memory to uninitialized GART !\n");
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return -EINVAL;
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}
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#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
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t = offset / AMDGPU_GPU_PAGE_SIZE;
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p = t / AMDGPU_GPU_PAGES_IN_CPU_PAGE;
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for (i = 0; i < pages; i++, p++)
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adev->gart.pages[p] = pagelist ? pagelist[i] : NULL;
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#endif
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if (!adev->gart.ptr)
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return 0;
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r = amdgpu_gart_map(adev, offset, pages, dma_addr, flags,
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adev->gart.ptr);
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if (r)
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return r;
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mb();
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amdgpu_asic_flush_hdp(adev, NULL);
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amdgpu_gmc_flush_gpu_tlb(adev, 0);
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return 0;
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}
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/**
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* amdgpu_gart_init - init the driver info for managing the gart
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate the dummy page and init the gart driver info (all asics).
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* Returns 0 for success, error for failure.
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*/
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int amdgpu_gart_init(struct amdgpu_device *adev)
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{
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int r;
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if (adev->dummy_page_addr)
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return 0;
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/* We need PAGE_SIZE >= AMDGPU_GPU_PAGE_SIZE */
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if (PAGE_SIZE < AMDGPU_GPU_PAGE_SIZE) {
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DRM_ERROR("Page size is smaller than GPU page size!\n");
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return -EINVAL;
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}
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r = amdgpu_gart_dummy_page_init(adev);
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if (r)
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return r;
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/* Compute table size */
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|
|
adev->gart.num_cpu_pages = adev->gmc.gart_size / PAGE_SIZE;
|
||
|
|
adev->gart.num_gpu_pages = adev->gmc.gart_size / AMDGPU_GPU_PAGE_SIZE;
|
||
|
|
DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n",
|
||
|
|
adev->gart.num_cpu_pages, adev->gart.num_gpu_pages);
|
||
|
|
|
||
|
|
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
|
||
|
|
/* Allocate pages table */
|
||
|
|
adev->gart.pages = vzalloc(array_size(sizeof(void *),
|
||
|
|
adev->gart.num_cpu_pages));
|
||
|
|
if (adev->gart.pages == NULL)
|
||
|
|
return -ENOMEM;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* amdgpu_gart_fini - tear down the driver info for managing the gart
|
||
|
|
*
|
||
|
|
* @adev: amdgpu_device pointer
|
||
|
|
*
|
||
|
|
* Tear down the gart driver info and free the dummy page (all asics).
|
||
|
|
*/
|
||
|
|
void amdgpu_gart_fini(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
#ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS
|
||
|
|
vfree(adev->gart.pages);
|
||
|
|
adev->gart.pages = NULL;
|
||
|
|
#endif
|
||
|
|
amdgpu_gart_dummy_page_fini(adev);
|
||
|
|
}
|