88 lines
2.8 KiB
C
88 lines
2.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef PANEL_R66451_FHDP_DSI_CMD_120HZ_TIANMA
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#define PANEL_R66451_FHDP_DSI_CMD_120HZ_TIANMA
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#define REGFLAG_DELAY 0xFFFC
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#define REGFLAG_UDELAY 0xFFFB
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#define REGFLAG_END_OF_TABLE 0xFFFD
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#define REGFLAG_RESET_LOW 0xFFFE
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#define REGFLAG_RESET_HIGH 0xFFFF
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#define PANEL_CLOCK 414831
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#define FRAME_WIDTH 1080
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#define FRAME_HEIGHT 2340
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#define PHYSICAL_WIDTH 70200
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#define PHYSICAL_HEIGHT 152100
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#define DATA_RATE 800
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#define HSA 10
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#define HBP 20
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#define VSA 2
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#define VBP 8
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/*Parameter setting for mode 0 Start*/
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#define MODE_0_FPS 60
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#define MODE_0_VFP 20
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#define MODE_0_HFP 40
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#define MODE_0_DATA_RATE 800
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/*Parameter setting for mode 0 End*/
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/*Parameter setting for mode 1 Start*/
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#define MODE_1_FPS 90
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#define MODE_1_VFP 20
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#define MODE_1_HFP 40
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#define MODE_1_DATA_RATE 800
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/*Parameter setting for mode 1 End*/
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/*Parameter setting for mode 2 Start*/
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#define MODE_2_FPS 120
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#define MODE_2_VFP 20
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#define MODE_2_HFP 40
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#define MODE_2_DATA_RATE 800
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/*Parameter setting for mode 2 End*/
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/* DSC RELATED */
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#define DSC_ENABLE 1
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#define DSC_VER 17
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#define DSC_SLICE_MODE 1
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#define DSC_RGB_SWAP 0
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#define DSC_DSC_CFG 34
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#define DSC_RCT_ON 1
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#define DSC_BIT_PER_CHANNEL 8
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#define DSC_DSC_LINE_BUF_DEPTH 9
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#define DSC_BP_ENABLE 1
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#define DSC_BIT_PER_PIXEL 128
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//define DSC_PIC_HEIGHT
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//define DSC_PIC_WIDTH
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#define DSC_SLICE_HEIGHT 20
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#define DSC_SLICE_WIDTH 540
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#define DSC_CHUNK_SIZE 540
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#define DSC_XMIT_DELAY 512
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#define DSC_DEC_DELAY 526
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#define DSC_SCALE_VALUE 32
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#define DSC_INCREMENT_INTERVAL 488
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#define DSC_DECREMENT_INTERVAL 7
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#define DSC_LINE_BPG_OFFSET 12
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#define DSC_NFL_BPG_OFFSET 1294
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#define DSC_SLICE_BPG_OFFSET 1302
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#define DSC_INITIAL_OFFSET 6144
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#define DSC_FINAL_OFFSET 4336
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#define DSC_FLATNESS_MINQP 3
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#define DSC_FLATNESS_MAXQP 12
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#define DSC_RC_MODEL_SIZE 8192
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#define DSC_RC_EDGE_FACTOR 6
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#define DSC_RC_QUANT_INCR_LIMIT0 11
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#define DSC_RC_QUANT_INCR_LIMIT1 11
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#define DSC_RC_TGT_OFFSET_HI 3
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#define DSC_RC_TGT_OFFSET_LO 3
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#endif //end of PANEL_R66451_FHDP_DSI_CMD_120HZ_TIANMA
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