293 lines
8.3 KiB
C
293 lines
8.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016 Allwinnertech Co., Ltd.
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* Copyright (C) 2017-2018 Bootlin
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*/
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#include <linux/bitops.h>
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#include <linux/clk.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "sun6i_mipi_dsi.h"
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#define SUN6I_DPHY_GCTL_REG 0x00
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#define SUN6I_DPHY_GCTL_LANE_NUM(n) ((((n) - 1) & 3) << 4)
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#define SUN6I_DPHY_GCTL_EN BIT(0)
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#define SUN6I_DPHY_TX_CTL_REG 0x04
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#define SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT BIT(28)
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#define SUN6I_DPHY_TX_TIME0_REG 0x10
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#define SUN6I_DPHY_TX_TIME0_HS_TRAIL(n) (((n) & 0xff) << 24)
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#define SUN6I_DPHY_TX_TIME0_HS_PREPARE(n) (((n) & 0xff) << 16)
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#define SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(n) ((n) & 0xff)
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#define SUN6I_DPHY_TX_TIME1_REG 0x14
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#define SUN6I_DPHY_TX_TIME1_CLK_POST(n) (((n) & 0xff) << 24)
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#define SUN6I_DPHY_TX_TIME1_CLK_PRE(n) (((n) & 0xff) << 16)
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#define SUN6I_DPHY_TX_TIME1_CLK_ZERO(n) (((n) & 0xff) << 8)
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#define SUN6I_DPHY_TX_TIME1_CLK_PREPARE(n) ((n) & 0xff)
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#define SUN6I_DPHY_TX_TIME2_REG 0x18
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#define SUN6I_DPHY_TX_TIME2_CLK_TRAIL(n) ((n) & 0xff)
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#define SUN6I_DPHY_TX_TIME3_REG 0x1c
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#define SUN6I_DPHY_TX_TIME4_REG 0x20
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#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(n) (((n) & 0xff) << 8)
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#define SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(n) ((n) & 0xff)
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#define SUN6I_DPHY_ANA0_REG 0x4c
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#define SUN6I_DPHY_ANA0_REG_PWS BIT(31)
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#define SUN6I_DPHY_ANA0_REG_DMPC BIT(28)
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#define SUN6I_DPHY_ANA0_REG_DMPD(n) (((n) & 0xf) << 24)
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#define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
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#define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
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#define SUN6I_DPHY_ANA1_REG 0x50
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#define SUN6I_DPHY_ANA1_REG_VTTMODE BIT(31)
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#define SUN6I_DPHY_ANA1_REG_CSMPS(n) (((n) & 3) << 28)
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#define SUN6I_DPHY_ANA1_REG_SVTT(n) (((n) & 0xf) << 24)
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#define SUN6I_DPHY_ANA2_REG 0x54
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#define SUN6I_DPHY_ANA2_EN_P2S_CPU(n) (((n) & 0xf) << 24)
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#define SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK GENMASK(27, 24)
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#define SUN6I_DPHY_ANA2_EN_CK_CPU BIT(4)
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#define SUN6I_DPHY_ANA2_REG_ENIB BIT(1)
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#define SUN6I_DPHY_ANA3_REG 0x58
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#define SUN6I_DPHY_ANA3_EN_VTTD(n) (((n) & 0xf) << 28)
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#define SUN6I_DPHY_ANA3_EN_VTTD_MASK GENMASK(31, 28)
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#define SUN6I_DPHY_ANA3_EN_VTTC BIT(27)
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#define SUN6I_DPHY_ANA3_EN_DIV BIT(26)
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#define SUN6I_DPHY_ANA3_EN_LDOC BIT(25)
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#define SUN6I_DPHY_ANA3_EN_LDOD BIT(24)
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#define SUN6I_DPHY_ANA3_EN_LDOR BIT(18)
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#define SUN6I_DPHY_ANA4_REG 0x5c
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#define SUN6I_DPHY_ANA4_REG_DMPLVC BIT(24)
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#define SUN6I_DPHY_ANA4_REG_DMPLVD(n) (((n) & 0xf) << 20)
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#define SUN6I_DPHY_ANA4_REG_CKDV(n) (((n) & 0x1f) << 12)
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#define SUN6I_DPHY_ANA4_REG_TMSC(n) (((n) & 3) << 10)
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#define SUN6I_DPHY_ANA4_REG_TMSD(n) (((n) & 3) << 8)
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#define SUN6I_DPHY_ANA4_REG_TXDNSC(n) (((n) & 3) << 6)
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#define SUN6I_DPHY_ANA4_REG_TXDNSD(n) (((n) & 3) << 4)
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#define SUN6I_DPHY_ANA4_REG_TXPUSC(n) (((n) & 3) << 2)
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#define SUN6I_DPHY_ANA4_REG_TXPUSD(n) ((n) & 3)
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#define SUN6I_DPHY_DBG5_REG 0xf4
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int sun6i_dphy_init(struct sun6i_dphy *dphy, unsigned int lanes)
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{
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reset_control_deassert(dphy->reset);
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clk_prepare_enable(dphy->mod_clk);
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clk_set_rate_exclusive(dphy->mod_clk, 150000000);
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regmap_write(dphy->regs, SUN6I_DPHY_TX_CTL_REG,
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SUN6I_DPHY_TX_CTL_HS_TX_CLK_CONT);
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regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME0_REG,
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SUN6I_DPHY_TX_TIME0_LP_CLK_DIV(14) |
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SUN6I_DPHY_TX_TIME0_HS_PREPARE(6) |
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SUN6I_DPHY_TX_TIME0_HS_TRAIL(10));
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regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME1_REG,
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SUN6I_DPHY_TX_TIME1_CLK_PREPARE(7) |
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SUN6I_DPHY_TX_TIME1_CLK_ZERO(50) |
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SUN6I_DPHY_TX_TIME1_CLK_PRE(3) |
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SUN6I_DPHY_TX_TIME1_CLK_POST(10));
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regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME2_REG,
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SUN6I_DPHY_TX_TIME2_CLK_TRAIL(30));
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regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME3_REG, 0);
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regmap_write(dphy->regs, SUN6I_DPHY_TX_TIME4_REG,
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SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) |
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SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3));
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regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG,
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SUN6I_DPHY_GCTL_LANE_NUM(lanes) |
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SUN6I_DPHY_GCTL_EN);
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return 0;
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}
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int sun6i_dphy_power_on(struct sun6i_dphy *dphy, unsigned int lanes)
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{
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u8 lanes_mask = GENMASK(lanes - 1, 0);
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regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
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SUN6I_DPHY_ANA0_REG_PWS |
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SUN6I_DPHY_ANA0_REG_DMPC |
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SUN6I_DPHY_ANA0_REG_SLV(7) |
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SUN6I_DPHY_ANA0_REG_DMPD(lanes_mask) |
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SUN6I_DPHY_ANA0_REG_DEN(lanes_mask));
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regmap_write(dphy->regs, SUN6I_DPHY_ANA1_REG,
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SUN6I_DPHY_ANA1_REG_CSMPS(1) |
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SUN6I_DPHY_ANA1_REG_SVTT(7));
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regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
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SUN6I_DPHY_ANA4_REG_CKDV(1) |
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SUN6I_DPHY_ANA4_REG_TMSC(1) |
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SUN6I_DPHY_ANA4_REG_TMSD(1) |
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SUN6I_DPHY_ANA4_REG_TXDNSC(1) |
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SUN6I_DPHY_ANA4_REG_TXDNSD(1) |
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SUN6I_DPHY_ANA4_REG_TXPUSC(1) |
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SUN6I_DPHY_ANA4_REG_TXPUSD(1) |
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SUN6I_DPHY_ANA4_REG_DMPLVC |
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SUN6I_DPHY_ANA4_REG_DMPLVD(lanes_mask));
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regmap_write(dphy->regs, SUN6I_DPHY_ANA2_REG,
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SUN6I_DPHY_ANA2_REG_ENIB);
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udelay(5);
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regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
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SUN6I_DPHY_ANA3_EN_LDOR |
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SUN6I_DPHY_ANA3_EN_LDOC |
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SUN6I_DPHY_ANA3_EN_LDOD);
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udelay(1);
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regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
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SUN6I_DPHY_ANA3_EN_VTTC |
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SUN6I_DPHY_ANA3_EN_VTTD_MASK,
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SUN6I_DPHY_ANA3_EN_VTTC |
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SUN6I_DPHY_ANA3_EN_VTTD(lanes_mask));
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udelay(1);
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regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA3_REG,
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SUN6I_DPHY_ANA3_EN_DIV,
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SUN6I_DPHY_ANA3_EN_DIV);
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udelay(1);
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regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
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SUN6I_DPHY_ANA2_EN_CK_CPU,
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SUN6I_DPHY_ANA2_EN_CK_CPU);
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udelay(1);
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regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG,
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SUN6I_DPHY_ANA1_REG_VTTMODE,
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SUN6I_DPHY_ANA1_REG_VTTMODE);
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regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
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SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK,
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SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask));
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return 0;
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}
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int sun6i_dphy_power_off(struct sun6i_dphy *dphy)
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{
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regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA1_REG,
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SUN6I_DPHY_ANA1_REG_VTTMODE, 0);
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return 0;
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}
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int sun6i_dphy_exit(struct sun6i_dphy *dphy)
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{
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clk_rate_exclusive_put(dphy->mod_clk);
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clk_disable_unprepare(dphy->mod_clk);
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reset_control_assert(dphy->reset);
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return 0;
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}
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static struct regmap_config sun6i_dphy_regmap_config = {
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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.max_register = SUN6I_DPHY_DBG5_REG,
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.name = "mipi-dphy",
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};
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static const struct of_device_id sun6i_dphy_of_table[] = {
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{ .compatible = "allwinner,sun6i-a31-mipi-dphy" },
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{ }
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};
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int sun6i_dphy_probe(struct sun6i_dsi *dsi, struct device_node *node)
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{
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struct sun6i_dphy *dphy;
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struct resource res;
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void __iomem *regs;
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int ret;
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if (!of_match_node(sun6i_dphy_of_table, node)) {
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dev_err(dsi->dev, "Incompatible D-PHY\n");
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return -EINVAL;
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}
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dphy = devm_kzalloc(dsi->dev, sizeof(*dphy), GFP_KERNEL);
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if (!dphy)
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return -ENOMEM;
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ret = of_address_to_resource(node, 0, &res);
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if (ret) {
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dev_err(dsi->dev, "phy: Couldn't get our resources\n");
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return ret;
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}
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regs = devm_ioremap_resource(dsi->dev, &res);
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if (IS_ERR(regs)) {
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dev_err(dsi->dev, "Couldn't map the DPHY encoder registers\n");
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return PTR_ERR(regs);
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}
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dphy->regs = devm_regmap_init_mmio(dsi->dev, regs,
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&sun6i_dphy_regmap_config);
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if (IS_ERR(dphy->regs)) {
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dev_err(dsi->dev, "Couldn't create the DPHY encoder regmap\n");
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return PTR_ERR(dphy->regs);
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}
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dphy->reset = of_reset_control_get_shared(node, NULL);
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if (IS_ERR(dphy->reset)) {
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dev_err(dsi->dev, "Couldn't get our reset line\n");
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return PTR_ERR(dphy->reset);
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}
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dphy->bus_clk = of_clk_get_by_name(node, "bus");
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if (IS_ERR(dphy->bus_clk)) {
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dev_err(dsi->dev, "Couldn't get the DPHY bus clock\n");
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ret = PTR_ERR(dphy->bus_clk);
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goto err_free_reset;
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}
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regmap_mmio_attach_clk(dphy->regs, dphy->bus_clk);
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dphy->mod_clk = of_clk_get_by_name(node, "mod");
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if (IS_ERR(dphy->mod_clk)) {
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dev_err(dsi->dev, "Couldn't get the DPHY mod clock\n");
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ret = PTR_ERR(dphy->mod_clk);
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goto err_free_bus;
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}
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dsi->dphy = dphy;
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return 0;
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err_free_bus:
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regmap_mmio_detach_clk(dphy->regs);
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clk_put(dphy->bus_clk);
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err_free_reset:
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reset_control_put(dphy->reset);
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return ret;
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}
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int sun6i_dphy_remove(struct sun6i_dsi *dsi)
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{
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struct sun6i_dphy *dphy = dsi->dphy;
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regmap_mmio_detach_clk(dphy->regs);
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clk_put(dphy->mod_clk);
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clk_put(dphy->bus_clk);
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reset_control_put(dphy->reset);
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return 0;
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}
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