592 lines
15 KiB
C
592 lines
15 KiB
C
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/* $Id: hfc_2bs0.c,v 1.20.2.6 2004/02/11 13:21:33 keil Exp $
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*
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* specific routines for CCD's HFC 2BS0
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*
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* Author Karsten Keil
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* Copyright by Karsten Keil <keil@isdn4linux.de>
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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*/
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#include <linux/init.h>
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#include "hisax.h"
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#include "hfc_2bs0.h"
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#include "isac.h"
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#include "isdnl1.h"
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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static inline int
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WaitForBusy(struct IsdnCardState *cs)
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{
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int to = 130;
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u_char val;
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while (!(cs->BC_Read_Reg(cs, HFC_STATUS, 0) & HFC_BUSY) && to) {
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val = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2 |
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(cs->hw.hfc.cip & 3));
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udelay(1);
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to--;
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}
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if (!to) {
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printk(KERN_WARNING "HiSax: %s timeout\n", __func__);
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return (0);
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} else
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return (to);
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}
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static inline int
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WaitNoBusy(struct IsdnCardState *cs)
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{
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int to = 125;
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while ((cs->BC_Read_Reg(cs, HFC_STATUS, 0) & HFC_BUSY) && to) {
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udelay(1);
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to--;
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}
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if (!to) {
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printk(KERN_WARNING "HiSax: waitforBusy timeout\n");
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return (0);
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} else
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return (to);
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}
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static int
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GetFreeFifoBytes(struct BCState *bcs)
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{
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int s;
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if (bcs->hw.hfc.f1 == bcs->hw.hfc.f2)
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return (bcs->cs->hw.hfc.fifosize);
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s = bcs->hw.hfc.send[bcs->hw.hfc.f1] - bcs->hw.hfc.send[bcs->hw.hfc.f2];
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if (s <= 0)
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s += bcs->cs->hw.hfc.fifosize;
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s = bcs->cs->hw.hfc.fifosize - s;
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return (s);
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}
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static int
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ReadZReg(struct BCState *bcs, u_char reg)
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{
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int val;
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WaitNoBusy(bcs->cs);
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val = 256 * bcs->cs->BC_Read_Reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_HIGH);
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WaitNoBusy(bcs->cs);
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val += bcs->cs->BC_Read_Reg(bcs->cs, HFC_DATA, reg | HFC_CIP | HFC_Z_LOW);
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return (val);
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}
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static void
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hfc_clear_fifo(struct BCState *bcs)
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{
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struct IsdnCardState *cs = bcs->cs;
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int idx, cnt;
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int rcnt, z1, z2;
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u_char cip, f1, f2;
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if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
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debugl1(cs, "hfc_clear_fifo");
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cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
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if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) {
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cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip);
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WaitForBusy(cs);
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}
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WaitNoBusy(cs);
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f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
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cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
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WaitNoBusy(cs);
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f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
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z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
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z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
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cnt = 32;
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while (((f1 != f2) || (z1 != z2)) && cnt--) {
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if (cs->debug & L1_DEB_HSCX)
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debugl1(cs, "hfc clear %d f1(%d) f2(%d)",
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bcs->channel, f1, f2);
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rcnt = z1 - z2;
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if (rcnt < 0)
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rcnt += cs->hw.hfc.fifosize;
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if (rcnt)
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rcnt++;
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if (cs->debug & L1_DEB_HSCX)
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debugl1(cs, "hfc clear %d z1(%x) z2(%x) cnt(%d)",
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bcs->channel, z1, z2, rcnt);
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cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
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idx = 0;
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while ((idx < rcnt) && WaitNoBusy(cs)) {
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cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
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idx++;
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}
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if (f1 != f2) {
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WaitNoBusy(cs);
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cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
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HFC_CHANNEL(bcs->channel));
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WaitForBusy(cs);
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}
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cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
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WaitNoBusy(cs);
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f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
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cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
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WaitNoBusy(cs);
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f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
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z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
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z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
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}
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return;
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}
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static struct sk_buff
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*
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hfc_empty_fifo(struct BCState *bcs, int count)
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{
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u_char *ptr;
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struct sk_buff *skb;
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struct IsdnCardState *cs = bcs->cs;
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int idx;
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int chksum;
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u_char stat, cip;
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if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO))
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debugl1(cs, "hfc_empty_fifo");
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idx = 0;
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if (count > HSCX_BUFMAX + 3) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "hfc_empty_fifo: incoming packet too large");
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cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
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while ((idx++ < count) && WaitNoBusy(cs))
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cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
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WaitNoBusy(cs);
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stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
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HFC_CHANNEL(bcs->channel));
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WaitForBusy(cs);
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return (NULL);
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}
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if ((count < 4) && (bcs->mode != L1_MODE_TRANS)) {
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if (cs->debug & L1_DEB_WARN)
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debugl1(cs, "hfc_empty_fifo: incoming packet too small");
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cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
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while ((idx++ < count) && WaitNoBusy(cs))
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cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
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WaitNoBusy(cs);
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stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
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HFC_CHANNEL(bcs->channel));
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WaitForBusy(cs);
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#ifdef ERROR_STATISTIC
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bcs->err_inv++;
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#endif
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return (NULL);
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}
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if (bcs->mode == L1_MODE_TRANS)
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count -= 1;
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else
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count -= 3;
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if (!(skb = dev_alloc_skb(count)))
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printk(KERN_WARNING "HFC: receive out of memory\n");
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else {
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ptr = skb_put(skb, count);
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idx = 0;
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cip = HFC_CIP | HFC_FIFO_OUT | HFC_REC | HFC_CHANNEL(bcs->channel);
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while ((idx < count) && WaitNoBusy(cs)) {
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*ptr++ = cs->BC_Read_Reg(cs, HFC_DATA_NODEB, cip);
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idx++;
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}
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if (idx != count) {
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debugl1(cs, "RFIFO BUSY error");
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printk(KERN_WARNING "HFC FIFO channel %d BUSY Error\n", bcs->channel);
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dev_kfree_skb_any(skb);
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if (bcs->mode != L1_MODE_TRANS) {
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WaitNoBusy(cs);
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stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
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HFC_CHANNEL(bcs->channel));
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WaitForBusy(cs);
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}
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return (NULL);
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}
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if (bcs->mode != L1_MODE_TRANS) {
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WaitNoBusy(cs);
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chksum = (cs->BC_Read_Reg(cs, HFC_DATA, cip) << 8);
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WaitNoBusy(cs);
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chksum += cs->BC_Read_Reg(cs, HFC_DATA, cip);
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WaitNoBusy(cs);
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stat = cs->BC_Read_Reg(cs, HFC_DATA, cip);
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if (cs->debug & L1_DEB_HSCX)
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debugl1(cs, "hfc_empty_fifo %d chksum %x stat %x",
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bcs->channel, chksum, stat);
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if (stat) {
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debugl1(cs, "FIFO CRC error");
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dev_kfree_skb_any(skb);
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skb = NULL;
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#ifdef ERROR_STATISTIC
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bcs->err_crc++;
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#endif
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}
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WaitNoBusy(cs);
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stat = cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F2_INC | HFC_REC |
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HFC_CHANNEL(bcs->channel));
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WaitForBusy(cs);
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}
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}
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return (skb);
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}
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static void
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hfc_fill_fifo(struct BCState *bcs)
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{
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struct IsdnCardState *cs = bcs->cs;
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int idx, fcnt;
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int count;
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int z1, z2;
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u_char cip;
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if (!bcs->tx_skb)
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return;
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if (bcs->tx_skb->len <= 0)
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return;
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cip = HFC_CIP | HFC_F1 | HFC_SEND | HFC_CHANNEL(bcs->channel);
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if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) {
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cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip);
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WaitForBusy(cs);
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}
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WaitNoBusy(cs);
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if (bcs->mode != L1_MODE_TRANS) {
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bcs->hw.hfc.f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
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cip = HFC_CIP | HFC_F2 | HFC_SEND | HFC_CHANNEL(bcs->channel);
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WaitNoBusy(cs);
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bcs->hw.hfc.f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
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bcs->hw.hfc.send[bcs->hw.hfc.f1] = ReadZReg(bcs, HFC_Z1 | HFC_SEND | HFC_CHANNEL(bcs->channel));
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if (cs->debug & L1_DEB_HSCX)
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debugl1(cs, "hfc_fill_fifo %d f1(%d) f2(%d) z1(%x)",
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bcs->channel, bcs->hw.hfc.f1, bcs->hw.hfc.f2,
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bcs->hw.hfc.send[bcs->hw.hfc.f1]);
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fcnt = bcs->hw.hfc.f1 - bcs->hw.hfc.f2;
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if (fcnt < 0)
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fcnt += 32;
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if (fcnt > 30) {
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if (cs->debug & L1_DEB_HSCX)
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debugl1(cs, "hfc_fill_fifo more as 30 frames");
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return;
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}
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count = GetFreeFifoBytes(bcs);
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}
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else {
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WaitForBusy(cs);
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z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
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z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
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count = z1 - z2;
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if (count < 0)
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count += cs->hw.hfc.fifosize;
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} /* L1_MODE_TRANS */
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if (cs->debug & L1_DEB_HSCX)
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debugl1(cs, "hfc_fill_fifo %d count(%u/%d)",
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bcs->channel, bcs->tx_skb->len,
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count);
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if (count < bcs->tx_skb->len) {
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if (cs->debug & L1_DEB_HSCX)
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debugl1(cs, "hfc_fill_fifo no fifo mem");
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return;
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}
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cip = HFC_CIP | HFC_FIFO_IN | HFC_SEND | HFC_CHANNEL(bcs->channel);
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idx = 0;
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while ((idx < bcs->tx_skb->len) && WaitNoBusy(cs))
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cs->BC_Write_Reg(cs, HFC_DATA_NODEB, cip, bcs->tx_skb->data[idx++]);
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if (idx != bcs->tx_skb->len) {
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debugl1(cs, "FIFO Send BUSY error");
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printk(KERN_WARNING "HFC S FIFO channel %d BUSY Error\n", bcs->channel);
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} else {
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count = bcs->tx_skb->len;
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bcs->tx_cnt -= count;
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if (PACKET_NOACK == bcs->tx_skb->pkt_type)
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count = -1;
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dev_kfree_skb_any(bcs->tx_skb);
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bcs->tx_skb = NULL;
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if (bcs->mode != L1_MODE_TRANS) {
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WaitForBusy(cs);
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WaitNoBusy(cs);
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cs->BC_Read_Reg(cs, HFC_DATA, HFC_CIP | HFC_F1_INC | HFC_SEND | HFC_CHANNEL(bcs->channel));
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}
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if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) &&
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(count >= 0)) {
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u_long flags;
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spin_lock_irqsave(&bcs->aclock, flags);
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bcs->ackcnt += count;
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spin_unlock_irqrestore(&bcs->aclock, flags);
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schedule_event(bcs, B_ACKPENDING);
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}
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test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
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}
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
main_irq_hfc(struct BCState *bcs)
|
||
|
|
{
|
||
|
|
struct IsdnCardState *cs = bcs->cs;
|
||
|
|
int z1, z2, rcnt;
|
||
|
|
u_char f1, f2, cip;
|
||
|
|
int receive, transmit, count = 5;
|
||
|
|
struct sk_buff *skb;
|
||
|
|
|
||
|
|
Begin:
|
||
|
|
count--;
|
||
|
|
cip = HFC_CIP | HFC_F1 | HFC_REC | HFC_CHANNEL(bcs->channel);
|
||
|
|
if ((cip & 0xc3) != (cs->hw.hfc.cip & 0xc3)) {
|
||
|
|
cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip);
|
||
|
|
WaitForBusy(cs);
|
||
|
|
}
|
||
|
|
WaitNoBusy(cs);
|
||
|
|
receive = 0;
|
||
|
|
if (bcs->mode == L1_MODE_HDLC) {
|
||
|
|
f1 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
|
||
|
|
cip = HFC_CIP | HFC_F2 | HFC_REC | HFC_CHANNEL(bcs->channel);
|
||
|
|
WaitNoBusy(cs);
|
||
|
|
f2 = cs->BC_Read_Reg(cs, HFC_DATA, cip);
|
||
|
|
if (f1 != f2) {
|
||
|
|
if (cs->debug & L1_DEB_HSCX)
|
||
|
|
debugl1(cs, "hfc rec %d f1(%d) f2(%d)",
|
||
|
|
bcs->channel, f1, f2);
|
||
|
|
receive = 1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if (receive || (bcs->mode == L1_MODE_TRANS)) {
|
||
|
|
WaitForBusy(cs);
|
||
|
|
z1 = ReadZReg(bcs, HFC_Z1 | HFC_REC | HFC_CHANNEL(bcs->channel));
|
||
|
|
z2 = ReadZReg(bcs, HFC_Z2 | HFC_REC | HFC_CHANNEL(bcs->channel));
|
||
|
|
rcnt = z1 - z2;
|
||
|
|
if (rcnt < 0)
|
||
|
|
rcnt += cs->hw.hfc.fifosize;
|
||
|
|
if ((bcs->mode == L1_MODE_HDLC) || (rcnt)) {
|
||
|
|
rcnt++;
|
||
|
|
if (cs->debug & L1_DEB_HSCX)
|
||
|
|
debugl1(cs, "hfc rec %d z1(%x) z2(%x) cnt(%d)",
|
||
|
|
bcs->channel, z1, z2, rcnt);
|
||
|
|
/* sti(); */
|
||
|
|
if ((skb = hfc_empty_fifo(bcs, rcnt))) {
|
||
|
|
skb_queue_tail(&bcs->rqueue, skb);
|
||
|
|
schedule_event(bcs, B_RCVBUFREADY);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
receive = 1;
|
||
|
|
}
|
||
|
|
if (bcs->tx_skb) {
|
||
|
|
transmit = 1;
|
||
|
|
test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
|
||
|
|
hfc_fill_fifo(bcs);
|
||
|
|
if (test_bit(BC_FLG_BUSY, &bcs->Flag))
|
||
|
|
transmit = 0;
|
||
|
|
} else {
|
||
|
|
if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) {
|
||
|
|
transmit = 1;
|
||
|
|
test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
|
||
|
|
hfc_fill_fifo(bcs);
|
||
|
|
if (test_bit(BC_FLG_BUSY, &bcs->Flag))
|
||
|
|
transmit = 0;
|
||
|
|
} else {
|
||
|
|
transmit = 0;
|
||
|
|
schedule_event(bcs, B_XMTBUFREADY);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
if ((receive || transmit) && count)
|
||
|
|
goto Begin;
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
mode_hfc(struct BCState *bcs, int mode, int bc)
|
||
|
|
{
|
||
|
|
struct IsdnCardState *cs = bcs->cs;
|
||
|
|
|
||
|
|
if (cs->debug & L1_DEB_HSCX)
|
||
|
|
debugl1(cs, "HFC 2BS0 mode %d bchan %d/%d",
|
||
|
|
mode, bc, bcs->channel);
|
||
|
|
bcs->mode = mode;
|
||
|
|
bcs->channel = bc;
|
||
|
|
|
||
|
|
switch (mode) {
|
||
|
|
case (L1_MODE_NULL):
|
||
|
|
if (bc) {
|
||
|
|
cs->hw.hfc.ctmt &= ~1;
|
||
|
|
cs->hw.hfc.isac_spcr &= ~0x03;
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
cs->hw.hfc.ctmt &= ~2;
|
||
|
|
cs->hw.hfc.isac_spcr &= ~0x0c;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case (L1_MODE_TRANS):
|
||
|
|
cs->hw.hfc.ctmt &= ~(1 << bc); /* set HDLC mode */
|
||
|
|
cs->BC_Write_Reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt);
|
||
|
|
hfc_clear_fifo(bcs); /* complete fifo clear */
|
||
|
|
if (bc) {
|
||
|
|
cs->hw.hfc.ctmt |= 1;
|
||
|
|
cs->hw.hfc.isac_spcr &= ~0x03;
|
||
|
|
cs->hw.hfc.isac_spcr |= 0x02;
|
||
|
|
} else {
|
||
|
|
cs->hw.hfc.ctmt |= 2;
|
||
|
|
cs->hw.hfc.isac_spcr &= ~0x0c;
|
||
|
|
cs->hw.hfc.isac_spcr |= 0x08;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
case (L1_MODE_HDLC):
|
||
|
|
if (bc) {
|
||
|
|
cs->hw.hfc.ctmt &= ~1;
|
||
|
|
cs->hw.hfc.isac_spcr &= ~0x03;
|
||
|
|
cs->hw.hfc.isac_spcr |= 0x02;
|
||
|
|
} else {
|
||
|
|
cs->hw.hfc.ctmt &= ~2;
|
||
|
|
cs->hw.hfc.isac_spcr &= ~0x0c;
|
||
|
|
cs->hw.hfc.isac_spcr |= 0x08;
|
||
|
|
}
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
cs->BC_Write_Reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt);
|
||
|
|
cs->writeisac(cs, ISAC_SPCR, cs->hw.hfc.isac_spcr);
|
||
|
|
if (mode == L1_MODE_HDLC)
|
||
|
|
hfc_clear_fifo(bcs);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
hfc_l2l1(struct PStack *st, int pr, void *arg)
|
||
|
|
{
|
||
|
|
struct BCState *bcs = st->l1.bcs;
|
||
|
|
struct sk_buff *skb = arg;
|
||
|
|
u_long flags;
|
||
|
|
|
||
|
|
switch (pr) {
|
||
|
|
case (PH_DATA | REQUEST):
|
||
|
|
spin_lock_irqsave(&bcs->cs->lock, flags);
|
||
|
|
if (bcs->tx_skb) {
|
||
|
|
skb_queue_tail(&bcs->squeue, skb);
|
||
|
|
} else {
|
||
|
|
bcs->tx_skb = skb;
|
||
|
|
test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
|
||
|
|
bcs->cs->BC_Send_Data(bcs);
|
||
|
|
}
|
||
|
|
spin_unlock_irqrestore(&bcs->cs->lock, flags);
|
||
|
|
break;
|
||
|
|
case (PH_PULL | INDICATION):
|
||
|
|
spin_lock_irqsave(&bcs->cs->lock, flags);
|
||
|
|
if (bcs->tx_skb) {
|
||
|
|
printk(KERN_WARNING "hfc_l2l1: this shouldn't happen\n");
|
||
|
|
} else {
|
||
|
|
test_and_set_bit(BC_FLG_BUSY, &bcs->Flag);
|
||
|
|
bcs->tx_skb = skb;
|
||
|
|
bcs->cs->BC_Send_Data(bcs);
|
||
|
|
}
|
||
|
|
spin_unlock_irqrestore(&bcs->cs->lock, flags);
|
||
|
|
break;
|
||
|
|
case (PH_PULL | REQUEST):
|
||
|
|
if (!bcs->tx_skb) {
|
||
|
|
test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
||
|
|
st->l1.l1l2(st, PH_PULL | CONFIRM, NULL);
|
||
|
|
} else
|
||
|
|
test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags);
|
||
|
|
break;
|
||
|
|
case (PH_ACTIVATE | REQUEST):
|
||
|
|
spin_lock_irqsave(&bcs->cs->lock, flags);
|
||
|
|
test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag);
|
||
|
|
mode_hfc(bcs, st->l1.mode, st->l1.bc);
|
||
|
|
spin_unlock_irqrestore(&bcs->cs->lock, flags);
|
||
|
|
l1_msg_b(st, pr, arg);
|
||
|
|
break;
|
||
|
|
case (PH_DEACTIVATE | REQUEST):
|
||
|
|
l1_msg_b(st, pr, arg);
|
||
|
|
break;
|
||
|
|
case (PH_DEACTIVATE | CONFIRM):
|
||
|
|
spin_lock_irqsave(&bcs->cs->lock, flags);
|
||
|
|
test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag);
|
||
|
|
test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
|
||
|
|
mode_hfc(bcs, 0, st->l1.bc);
|
||
|
|
spin_unlock_irqrestore(&bcs->cs->lock, flags);
|
||
|
|
st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
static void
|
||
|
|
close_hfcstate(struct BCState *bcs)
|
||
|
|
{
|
||
|
|
mode_hfc(bcs, 0, bcs->channel);
|
||
|
|
if (test_bit(BC_FLG_INIT, &bcs->Flag)) {
|
||
|
|
skb_queue_purge(&bcs->rqueue);
|
||
|
|
skb_queue_purge(&bcs->squeue);
|
||
|
|
if (bcs->tx_skb) {
|
||
|
|
dev_kfree_skb_any(bcs->tx_skb);
|
||
|
|
bcs->tx_skb = NULL;
|
||
|
|
test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
|
||
|
|
}
|
||
|
|
}
|
||
|
|
test_and_clear_bit(BC_FLG_INIT, &bcs->Flag);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
open_hfcstate(struct IsdnCardState *cs, struct BCState *bcs)
|
||
|
|
{
|
||
|
|
if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) {
|
||
|
|
skb_queue_head_init(&bcs->rqueue);
|
||
|
|
skb_queue_head_init(&bcs->squeue);
|
||
|
|
}
|
||
|
|
bcs->tx_skb = NULL;
|
||
|
|
test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag);
|
||
|
|
bcs->event = 0;
|
||
|
|
bcs->tx_cnt = 0;
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
setstack_hfc(struct PStack *st, struct BCState *bcs)
|
||
|
|
{
|
||
|
|
bcs->channel = st->l1.bc;
|
||
|
|
if (open_hfcstate(st->l1.hardware, bcs))
|
||
|
|
return (-1);
|
||
|
|
st->l1.bcs = bcs;
|
||
|
|
st->l2.l2l1 = hfc_l2l1;
|
||
|
|
setstack_manager(st);
|
||
|
|
bcs->st = st;
|
||
|
|
setstack_l1_B(st);
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
init_send(struct BCState *bcs)
|
||
|
|
{
|
||
|
|
int i;
|
||
|
|
|
||
|
|
bcs->hw.hfc.send = kmalloc_array(32, sizeof(unsigned int), GFP_ATOMIC);
|
||
|
|
if (!bcs->hw.hfc.send) {
|
||
|
|
printk(KERN_WARNING
|
||
|
|
"HiSax: No memory for hfc.send\n");
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
for (i = 0; i < 32; i++)
|
||
|
|
bcs->hw.hfc.send[i] = 0x1fff;
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
inithfc(struct IsdnCardState *cs)
|
||
|
|
{
|
||
|
|
init_send(&cs->bcs[0]);
|
||
|
|
init_send(&cs->bcs[1]);
|
||
|
|
cs->BC_Send_Data = &hfc_fill_fifo;
|
||
|
|
cs->bcs[0].BC_SetStack = setstack_hfc;
|
||
|
|
cs->bcs[1].BC_SetStack = setstack_hfc;
|
||
|
|
cs->bcs[0].BC_Close = close_hfcstate;
|
||
|
|
cs->bcs[1].BC_Close = close_hfcstate;
|
||
|
|
mode_hfc(cs->bcs, 0, 0);
|
||
|
|
mode_hfc(cs->bcs + 1, 0, 0);
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
releasehfc(struct IsdnCardState *cs)
|
||
|
|
{
|
||
|
|
kfree(cs->bcs[0].hw.hfc.send);
|
||
|
|
cs->bcs[0].hw.hfc.send = NULL;
|
||
|
|
kfree(cs->bcs[1].hw.hfc.send);
|
||
|
|
cs->bcs[1].hw.hfc.send = NULL;
|
||
|
|
}
|