290 lines
6.9 KiB
C
290 lines
6.9 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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* Author: Sagy Shih <sagy.shih@mediatek.com>
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*/
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/kallsyms.h>
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#include <linux/cpu.h>
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#include <linux/smp.h>
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#include <linux/vmalloc.h>
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#include <linux/memblock.h>
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#include <linux/sched.h>
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#include <linux/delay.h>
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#include <asm/cacheflush.h>
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/* #include <mach/mtk_clkmgr.h> */
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <asm/setup.h>
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/* #include <mt-plat/dma.h> */
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#include <mt-plat/sync_write.h>
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#include <mt-plat/mtk_chip.h>
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#include <mt-plat/aee.h>
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#include <dramc_io.h>
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#include "mtk_dramc.h"
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#include "dramc.h"
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#define Reg_Sync_Writel(addr, val) writel(val, IOMEM(addr))
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#define Reg_Readl(addr) readl(IOMEM(addr))
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#ifdef LAST_DRAMC_IP_BASED
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static void __iomem *(*get_emi_base)(void);
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__weak unsigned int mt_dramc_ta_addr_set(unsigned int rank,
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unsigned int temp_addr)
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{
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return 0;
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}
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__weak unsigned int platform_support_dram_type(void)
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{
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return 0;
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}
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static int __init set_single_channel_test_angent(int channel)
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{
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void __iomem *dramc_ao_base = NULL;
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void __iomem *emi_base;
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unsigned int bit_scramble, bit_xor, bit_shift;
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unsigned int emi_cona, emi_conf;
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unsigned int channel_position, channel_num, channel_width = 0;
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unsigned int rank, temp, rank_max;
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unsigned int ddr_type;
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unsigned int base_reg[2] = { 0x94, 0x8c };
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phys_addr_t test_agent_base, rank_base;
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emi_base = get_emi_base();
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if (emi_base == NULL) {
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pr_err("[LastDRAMC] can't find EMI base\n");
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return -1;
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}
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emi_cona = readl(IOMEM(emi_base+0x000));
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emi_conf = readl(IOMEM(emi_base+0x028))>>8;
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channel_num = mt_dramc_chn_get(emi_cona);
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if (channel < 0 || channel >= channel_num) {
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pr_err("[LastDRAMC] invalid channel: %d\n", channel);
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return -1;
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}
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dramc_ao_base = mt_dramc_chn_base_get(channel);
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if (!dramc_ao_base) {
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pr_err("[LastDRAMC] no dramc_ao_base, skip channel %d\n",
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channel);
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return -1;
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}
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rank_max = mt_dramc_ta_support_ranks();
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if (rank_max > 2) {
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pr_err("[LastDRAMC] invalid rank num, rank_max %u\n",
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rank_max);
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return -1;
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}
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ddr_type = get_ddr_type();
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for (rank = 0; rank < rank_max; rank++) {
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rank_base = mt_dramc_rankbase_get(rank);
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if (!rank_base) {
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pr_err("[LastDRAMC] invalid base, rank %u\n",
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rank);
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return -1;
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}
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test_agent_base = mt_dramc_ta_reserve_addr(rank);
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if (!test_agent_base) {
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pr_err("[LastDRAMC] invalid addr, rank %u\n",
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rank);
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return -1;
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}
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test_agent_base = (test_agent_base - rank_base) & 0xFFFFFFFF;
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/* calculate DRAM base address (test_agent_base) */
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/* pr_info("[LastDRAMC] reserved address before emi: */
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/* %llx\n", test_agent_base); */
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for (bit_scramble = 11; bit_scramble < 17; bit_scramble++) {
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bit_xor = (emi_conf >> (4*(bit_scramble-11))) & 0xf;
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bit_xor &= test_agent_base >> 16;
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for (bit_shift = 0; bit_shift < 4; bit_shift++)
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test_agent_base ^= ((bit_xor>>bit_shift)&0x1)
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<< bit_scramble;
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}
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/* pr_info("[LastDRAMC] reserved address after emi: %llx\n", */
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/* test_agent_base); */
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if (channel_num > 1) {
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channel_position = mt_dramc_chp_get(emi_cona);
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for (channel_width = bit_shift = 0; bit_shift < 4;
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bit_shift++) {
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if ((1 << bit_shift) >= channel_num)
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break;
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channel_width++;
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}
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temp = ((test_agent_base &
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~(((0x1<<channel_width)-1)<<channel_position))
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>> channel_width);
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test_agent_base = temp |
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(test_agent_base & ((0x1<<channel_position)-1));
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}
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/* pr_info("[LastDRAMC] reserved address after emi: %llx\n", */
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/* test_agent_base); */
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/* set base address for test agent */
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temp = Reg_Readl(dramc_ao_base+base_reg[rank]) & 0xF;
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if ((ddr_type == TYPE_LPDDR4) || (ddr_type == TYPE_LPDDR4X))
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temp |= (test_agent_base>>1) & 0xFFFFFFF0;
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else if ((ddr_type == TYPE_LPDDR3) ||
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platform_support_dram_type())
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temp |= (test_agent_base) & 0xFFFFFFF0;
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else {
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pr_err("[LastDRAMC] undefined DRAM type\n");
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return -1;
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}
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if (!mt_dramc_ta_addr_set(rank, temp))
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Reg_Sync_Writel(dramc_ao_base+base_reg[rank], temp);
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}
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if (rank_max > 1)
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Reg_Sync_Writel(dramc_ao_base+0x9c,
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Reg_Readl(dramc_ao_base+0x9c) | (rank_max - 1));
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/* write test pattern */
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return 0;
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}
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static int __init last_dramc_test_agent_init(void)
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{
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void __iomem *emi_base;
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unsigned int emi_cona, i, channel_num;
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get_emi_base = (void __iomem *)symbol_get(mt_emi_base_get);
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if (get_emi_base == NULL) {
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pr_err("[LastDRAMC] mt_emi_base_get is NULL\n");
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return 0;
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}
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emi_base = get_emi_base();
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if (emi_base == NULL) {
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pr_err("[LastDRAMC] can't find EMI base\n");
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return 0;
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}
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emi_cona = readl(IOMEM(emi_base+0x000));
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channel_num = mt_dramc_chn_get(emi_cona);
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for (i = 0; i < channel_num; ++i)
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set_single_channel_test_angent(i);
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symbol_put(mt_emi_base_get);
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get_emi_base = NULL;
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return 0;
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}
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late_initcall(last_dramc_test_agent_init);
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static int dram_calib_perf_check_probe(struct platform_device *pdev)
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{
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struct device_node *node = pdev->dev.of_node;
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void __iomem *DRAMC_SRAM_DEBUG_BASE_ADDR;
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unsigned long val, last_dramc_ofs;
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if (node) {
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DRAMC_SRAM_DEBUG_BASE_ADDR = of_iomap(node, 0);
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} else {
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pr_err("can't find compatible node for dram_calib_perf_check\n");
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return -ENODEV;
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}
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last_dramc_ofs = 0;
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#ifdef LAST_DRAMC_SRAM_MGR
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for (last_dramc_ofs = 0; last_dramc_ofs < DBG_INFO_TYPE_MAX;
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last_dramc_ofs++) {
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val = Reg_Readl(DRAMC_SRAM_DEBUG_BASE_ADDR +
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(last_dramc_ofs * 4));
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if ((val >> 16) == LASTDRAMC_KEY)
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break;
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}
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if (last_dramc_ofs == DBG_INFO_TYPE_MAX) {
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pr_err("[DRAMC] lastdramc with sram mgr not found\n");
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return 0;
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}
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last_dramc_ofs = val & 0xFFFF;
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#else
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last_dramc_ofs = LAST_DRAMC_SRAM_SIZE;
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#endif
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val = Reg_Readl(DRAMC_SRAM_DEBUG_BASE_ADDR +
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last_dramc_ofs + DRAMC_STORAGE_API_ERR_OFFSET);
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if ((val & STORAGE_READ_API_MASK) == ERR_PL_UPDATED) {
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pr_err("[DRAMC] k time too long: PL updated (0x%08lx)\n", val);
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} else if (val != 0) {
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aee_kernel_warning_api(__FILE__, __LINE__,
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DB_OPT_DUMMY_DUMP, "DRAM Calibration Time",
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"k time too long: api error (0x%08lx)\n", val);
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pr_err("[DRAMC] k time too long: api error (0x%08lx)\n", val);
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} else {
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pr_info("[DRAMC] k time optimized\n");
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}
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return 0;
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}
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static const struct of_device_id dramc_sram_debug_match[] = {
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{ .compatible = "mediatek,dramc_sram_debug" },
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{}
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};
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static struct platform_driver dramc_sram_debug_drv = {
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.probe = dram_calib_perf_check_probe,
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.driver = {
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.name = "dramc_sram_debug",
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.bus = &platform_bus_type,
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.owner = THIS_MODULE,
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.of_match_table = dramc_sram_debug_match,
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}
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};
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static int __init dram_calib_perf_check(void)
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{
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int ret;
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ret = platform_driver_register(&dramc_sram_debug_drv);
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if (ret) {
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pr_err("%s:%d: platform_driver_register failed\n",
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__func__, __LINE__);
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return -ENODEV;
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}
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return 0;
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}
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/* NOTE: must be called after aed driver initialized
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*(i.e. must be later than arch_initcall)
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*/
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late_initcall(dram_calib_perf_check);
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#endif
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