33 lines
1,018 B
C
33 lines
1,018 B
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _DW_MMC_ZX_H_
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#define _DW_MMC_ZX_H_
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/* ZX296718 SoC specific DLL register offset. */
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#define LB_AON_EMMC_CFG_REG0 0x1B0
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#define LB_AON_EMMC_CFG_REG1 0x1B4
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#define LB_AON_EMMC_CFG_REG2 0x1B8
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/* LB_AON_EMMC_CFG_REG0 register defines */
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#define PARA_DLL_START(x) ((x) & 0xFF)
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#define PARA_DLL_START_MASK 0xFF
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#define DLL_REG_SET BIT(8)
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#define PARA_DLL_LOCK_NUM(x) (((x) & 7) << 16)
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#define PARA_DLL_LOCK_NUM_MASK (7 << 16)
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#define PARA_PHASE_DET_SEL(x) (((x) & 7) << 20)
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#define PARA_PHASE_DET_SEL_MASK (7 << 20)
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#define PARA_DLL_BYPASS_MODE BIT(23)
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#define PARA_HALF_CLK_MODE BIT(24)
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/* LB_AON_EMMC_CFG_REG1 register defines */
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#define READ_DQS_DELAY(x) ((x) & 0x7F)
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#define READ_DQS_DELAY_MASK (0x7F)
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#define READ_DQS_BYPASS_MODE BIT(7)
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#define CLK_SAMP_DELAY(x) (((x) & 0x7F) << 8)
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#define CLK_SAMP_DELAY_MASK (0x7F << 8)
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#define CLK_SAMP_BYPASS_MODE BIT(15)
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/* LB_AON_EMMC_CFG_REG2 register defines */
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#define ZX_DLL_LOCKED BIT(2)
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#endif /* _DW_MMC_ZX_H_ */
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