639 lines
12 KiB
C
639 lines
12 KiB
C
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/*****************************************************************************
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* *
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* File: cpl5_cmd.h *
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* $Revision: 1.6 $ *
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* $Date: 2005/06/21 18:29:47 $ *
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* Description: *
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* part of the Chelsio 10Gb Ethernet Driver. *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License, version 2, as *
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* published by the Free Software Foundation. *
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* *
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* You should have received a copy of the GNU General Public License along *
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* with this program; if not, see <http://www.gnu.org/licenses/>. *
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* *
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR IMPLIED *
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* WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF *
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
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* *
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* http://www.chelsio.com *
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* *
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* Copyright (c) 2003 - 2005 Chelsio Communications, Inc. *
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* All rights reserved. *
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* *
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* Maintainers: maintainers@chelsio.com *
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* *
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* Authors: Dimitrios Michailidis <dm@chelsio.com> *
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* Tina Yang <tainay@chelsio.com> *
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* Felix Marti <felix@chelsio.com> *
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* Scott Bardone <sbardone@chelsio.com> *
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* Kurt Ottaway <kottaway@chelsio.com> *
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* Frank DiMambro <frank@chelsio.com> *
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* *
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* History: *
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* *
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****************************************************************************/
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#ifndef _CXGB_CPL5_CMD_H_
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#define _CXGB_CPL5_CMD_H_
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#include <asm/byteorder.h>
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#if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
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#error "Adjust your <asm/byteorder.h> defines"
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#endif
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enum CPL_opcode {
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CPL_PASS_OPEN_REQ = 0x1,
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CPL_PASS_OPEN_RPL = 0x2,
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CPL_PASS_ESTABLISH = 0x3,
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CPL_PASS_ACCEPT_REQ = 0xE,
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CPL_PASS_ACCEPT_RPL = 0x4,
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CPL_ACT_OPEN_REQ = 0x5,
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CPL_ACT_OPEN_RPL = 0x6,
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CPL_CLOSE_CON_REQ = 0x7,
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CPL_CLOSE_CON_RPL = 0x8,
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CPL_CLOSE_LISTSRV_REQ = 0x9,
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CPL_CLOSE_LISTSRV_RPL = 0xA,
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CPL_ABORT_REQ = 0xB,
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CPL_ABORT_RPL = 0xC,
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CPL_PEER_CLOSE = 0xD,
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CPL_ACT_ESTABLISH = 0x17,
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CPL_GET_TCB = 0x24,
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CPL_GET_TCB_RPL = 0x25,
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CPL_SET_TCB = 0x26,
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CPL_SET_TCB_FIELD = 0x27,
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CPL_SET_TCB_RPL = 0x28,
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CPL_PCMD = 0x29,
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CPL_PCMD_READ = 0x31,
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CPL_PCMD_READ_RPL = 0x32,
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CPL_RX_DATA = 0xA0,
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CPL_RX_DATA_DDP = 0xA1,
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CPL_RX_DATA_ACK = 0xA3,
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CPL_RX_PKT = 0xAD,
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CPL_RX_ISCSI_HDR = 0xAF,
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CPL_TX_DATA_ACK = 0xB0,
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CPL_TX_DATA = 0xB1,
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CPL_TX_PKT = 0xB2,
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CPL_TX_PKT_LSO = 0xB6,
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CPL_RTE_DELETE_REQ = 0xC0,
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CPL_RTE_DELETE_RPL = 0xC1,
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CPL_RTE_WRITE_REQ = 0xC2,
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CPL_RTE_WRITE_RPL = 0xD3,
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CPL_RTE_READ_REQ = 0xC3,
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CPL_RTE_READ_RPL = 0xC4,
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CPL_L2T_WRITE_REQ = 0xC5,
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CPL_L2T_WRITE_RPL = 0xD4,
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CPL_L2T_READ_REQ = 0xC6,
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CPL_L2T_READ_RPL = 0xC7,
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CPL_SMT_WRITE_REQ = 0xC8,
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CPL_SMT_WRITE_RPL = 0xD5,
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CPL_SMT_READ_REQ = 0xC9,
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CPL_SMT_READ_RPL = 0xCA,
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CPL_ARP_MISS_REQ = 0xCD,
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CPL_ARP_MISS_RPL = 0xCE,
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CPL_MIGRATE_C2T_REQ = 0xDC,
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CPL_MIGRATE_C2T_RPL = 0xDD,
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CPL_ERROR = 0xD7,
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/* internal: driver -> TOM */
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CPL_MSS_CHANGE = 0xE1
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};
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#define NUM_CPL_CMDS 256
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enum CPL_error {
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CPL_ERR_NONE = 0,
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CPL_ERR_TCAM_PARITY = 1,
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CPL_ERR_TCAM_FULL = 3,
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CPL_ERR_CONN_RESET = 20,
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CPL_ERR_CONN_EXIST = 22,
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CPL_ERR_ARP_MISS = 23,
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CPL_ERR_BAD_SYN = 24,
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CPL_ERR_CONN_TIMEDOUT = 30,
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CPL_ERR_XMIT_TIMEDOUT = 31,
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CPL_ERR_PERSIST_TIMEDOUT = 32,
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CPL_ERR_FINWAIT2_TIMEDOUT = 33,
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CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
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CPL_ERR_ABORT_FAILED = 42,
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CPL_ERR_GENERAL = 99
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};
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enum {
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CPL_CONN_POLICY_AUTO = 0,
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CPL_CONN_POLICY_ASK = 1,
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CPL_CONN_POLICY_DENY = 3
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};
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enum {
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ULP_MODE_NONE = 0,
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ULP_MODE_TCPDDP = 1,
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ULP_MODE_ISCSI = 2,
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ULP_MODE_IWARP = 3,
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ULP_MODE_SSL = 4
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};
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enum {
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CPL_PASS_OPEN_ACCEPT,
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CPL_PASS_OPEN_REJECT
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};
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enum {
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CPL_ABORT_SEND_RST = 0,
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CPL_ABORT_NO_RST,
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CPL_ABORT_POST_CLOSE_REQ = 2
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};
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enum { // TX_PKT_LSO ethernet types
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CPL_ETH_II,
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CPL_ETH_II_VLAN,
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CPL_ETH_802_3,
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CPL_ETH_802_3_VLAN
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};
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union opcode_tid {
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u32 opcode_tid;
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u8 opcode;
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};
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#define S_OPCODE 24
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#define V_OPCODE(x) ((x) << S_OPCODE)
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#define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
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#define G_TID(x) ((x) & 0xFFFFFF)
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/* tid is assumed to be 24-bits */
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#define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
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#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
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/* extract the TID from a CPL command */
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#define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
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struct tcp_options {
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u16 mss;
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u8 wsf;
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#if defined(__LITTLE_ENDIAN_BITFIELD)
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u8 rsvd:4;
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u8 ecn:1;
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u8 sack:1;
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u8 tstamp:1;
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#else
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u8 tstamp:1;
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u8 sack:1;
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u8 ecn:1;
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u8 rsvd:4;
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#endif
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};
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struct cpl_pass_open_req {
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union opcode_tid ot;
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u16 local_port;
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u16 peer_port;
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u32 local_ip;
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u32 peer_ip;
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u32 opt0h;
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u32 opt0l;
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u32 peer_netmask;
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u32 opt1;
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};
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struct cpl_pass_open_rpl {
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union opcode_tid ot;
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u16 local_port;
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u16 peer_port;
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u32 local_ip;
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u32 peer_ip;
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u8 resvd[7];
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u8 status;
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};
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struct cpl_pass_establish {
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union opcode_tid ot;
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u16 local_port;
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u16 peer_port;
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u32 local_ip;
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u32 peer_ip;
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u32 tos_tid;
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u8 l2t_idx;
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u8 rsvd[3];
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u32 snd_isn;
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u32 rcv_isn;
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};
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struct cpl_pass_accept_req {
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union opcode_tid ot;
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u16 local_port;
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u16 peer_port;
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u32 local_ip;
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u32 peer_ip;
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u32 tos_tid;
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struct tcp_options tcp_options;
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u8 dst_mac[6];
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u16 vlan_tag;
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u8 src_mac[6];
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u8 rsvd[2];
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u32 rcv_isn;
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u32 unknown_tcp_options;
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};
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struct cpl_pass_accept_rpl {
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union opcode_tid ot;
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u32 rsvd0;
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u32 rsvd1;
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u32 peer_ip;
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u32 opt0h;
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union {
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u32 opt0l;
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struct {
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u8 rsvd[3];
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u8 status;
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};
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};
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};
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struct cpl_act_open_req {
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union opcode_tid ot;
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u16 local_port;
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u16 peer_port;
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u32 local_ip;
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u32 peer_ip;
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u32 opt0h;
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u32 opt0l;
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u32 iff_vlantag;
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u32 rsvd;
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};
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struct cpl_act_open_rpl {
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union opcode_tid ot;
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u16 local_port;
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u16 peer_port;
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u32 local_ip;
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u32 peer_ip;
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u32 new_tid;
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u8 rsvd[3];
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u8 status;
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};
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struct cpl_act_establish {
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union opcode_tid ot;
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u16 local_port;
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u16 peer_port;
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u32 local_ip;
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u32 peer_ip;
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u32 tos_tid;
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u32 rsvd;
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u32 snd_isn;
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u32 rcv_isn;
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};
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struct cpl_get_tcb {
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union opcode_tid ot;
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u32 rsvd;
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};
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struct cpl_get_tcb_rpl {
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union opcode_tid ot;
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u16 len;
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u8 rsvd;
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u8 status;
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};
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struct cpl_set_tcb {
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union opcode_tid ot;
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u16 len;
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u16 rsvd;
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};
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struct cpl_set_tcb_field {
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union opcode_tid ot;
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u8 rsvd[3];
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u8 offset;
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u32 mask;
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u32 val;
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};
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struct cpl_set_tcb_rpl {
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union opcode_tid ot;
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u8 rsvd[3];
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u8 status;
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};
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struct cpl_pcmd {
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union opcode_tid ot;
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u16 dlen_in;
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u16 dlen_out;
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u32 pcmd_parm[2];
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};
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struct cpl_pcmd_read {
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union opcode_tid ot;
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u32 rsvd1;
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u16 rsvd2;
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u32 addr;
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u16 len;
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};
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struct cpl_pcmd_read_rpl {
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union opcode_tid ot;
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u16 len;
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};
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struct cpl_close_con_req {
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union opcode_tid ot;
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u32 rsvd;
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};
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struct cpl_close_con_rpl {
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union opcode_tid ot;
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u8 rsvd[3];
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u8 status;
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u32 snd_nxt;
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u32 rcv_nxt;
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};
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struct cpl_close_listserv_req {
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union opcode_tid ot;
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u32 rsvd;
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};
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struct cpl_close_listserv_rpl {
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union opcode_tid ot;
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u8 rsvd[3];
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u8 status;
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};
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struct cpl_abort_req {
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union opcode_tid ot;
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u32 rsvd0;
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u8 rsvd1;
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u8 cmd;
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u8 rsvd2[6];
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};
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struct cpl_abort_rpl {
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union opcode_tid ot;
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u32 rsvd0;
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u8 rsvd1;
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u8 status;
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u8 rsvd2[6];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_peer_close {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u32 rsvd;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_tx_data {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u32 len;
|
||
|
|
u32 rsvd0;
|
||
|
|
u16 urg;
|
||
|
|
u16 flags;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_tx_data_ack {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u32 ack_seq;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_rx_data {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u32 len;
|
||
|
|
u32 seq;
|
||
|
|
u16 urg;
|
||
|
|
u8 rsvd;
|
||
|
|
u8 status;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_rx_data_ack {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u32 credit;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_rx_data_ddp {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u32 len;
|
||
|
|
u32 seq;
|
||
|
|
u32 nxt_seq;
|
||
|
|
u32 ulp_crc;
|
||
|
|
u16 ddp_status;
|
||
|
|
u8 rsvd;
|
||
|
|
u8 status;
|
||
|
|
};
|
||
|
|
|
||
|
|
/*
|
||
|
|
* We want this header's alignment to be no more stringent than 2-byte aligned.
|
||
|
|
* All fields are u8 or u16 except for the length. However that field is not
|
||
|
|
* used so we break it into 2 16-bit parts to easily meet our alignment needs.
|
||
|
|
*/
|
||
|
|
struct cpl_tx_pkt {
|
||
|
|
u8 opcode;
|
||
|
|
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
||
|
|
u8 iff:4;
|
||
|
|
u8 ip_csum_dis:1;
|
||
|
|
u8 l4_csum_dis:1;
|
||
|
|
u8 vlan_valid:1;
|
||
|
|
u8 rsvd:1;
|
||
|
|
#else
|
||
|
|
u8 rsvd:1;
|
||
|
|
u8 vlan_valid:1;
|
||
|
|
u8 l4_csum_dis:1;
|
||
|
|
u8 ip_csum_dis:1;
|
||
|
|
u8 iff:4;
|
||
|
|
#endif
|
||
|
|
u16 vlan;
|
||
|
|
u16 len_hi;
|
||
|
|
u16 len_lo;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_tx_pkt_lso {
|
||
|
|
u8 opcode;
|
||
|
|
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
||
|
|
u8 iff:4;
|
||
|
|
u8 ip_csum_dis:1;
|
||
|
|
u8 l4_csum_dis:1;
|
||
|
|
u8 vlan_valid:1;
|
||
|
|
u8 :1;
|
||
|
|
#else
|
||
|
|
u8 :1;
|
||
|
|
u8 vlan_valid:1;
|
||
|
|
u8 l4_csum_dis:1;
|
||
|
|
u8 ip_csum_dis:1;
|
||
|
|
u8 iff:4;
|
||
|
|
#endif
|
||
|
|
u16 vlan;
|
||
|
|
__be32 len;
|
||
|
|
|
||
|
|
u8 rsvd[5];
|
||
|
|
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
||
|
|
u8 tcp_hdr_words:4;
|
||
|
|
u8 ip_hdr_words:4;
|
||
|
|
#else
|
||
|
|
u8 ip_hdr_words:4;
|
||
|
|
u8 tcp_hdr_words:4;
|
||
|
|
#endif
|
||
|
|
__be16 eth_type_mss;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_rx_pkt {
|
||
|
|
u8 opcode;
|
||
|
|
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
||
|
|
u8 iff:4;
|
||
|
|
u8 csum_valid:1;
|
||
|
|
u8 bad_pkt:1;
|
||
|
|
u8 vlan_valid:1;
|
||
|
|
u8 rsvd:1;
|
||
|
|
#else
|
||
|
|
u8 rsvd:1;
|
||
|
|
u8 vlan_valid:1;
|
||
|
|
u8 bad_pkt:1;
|
||
|
|
u8 csum_valid:1;
|
||
|
|
u8 iff:4;
|
||
|
|
#endif
|
||
|
|
u16 csum;
|
||
|
|
u16 vlan;
|
||
|
|
u16 len;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_l2t_write_req {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u32 params;
|
||
|
|
u8 rsvd1[2];
|
||
|
|
u8 dst_mac[6];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_l2t_write_rpl {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u8 status;
|
||
|
|
u8 rsvd[3];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_l2t_read_req {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u8 rsvd[3];
|
||
|
|
u8 l2t_idx;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_l2t_read_rpl {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u32 params;
|
||
|
|
u8 rsvd1[2];
|
||
|
|
u8 dst_mac[6];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_smt_write_req {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u8 rsvd0;
|
||
|
|
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
||
|
|
u8 rsvd1:1;
|
||
|
|
u8 mtu_idx:3;
|
||
|
|
u8 iff:4;
|
||
|
|
#else
|
||
|
|
u8 iff:4;
|
||
|
|
u8 mtu_idx:3;
|
||
|
|
u8 rsvd1:1;
|
||
|
|
#endif
|
||
|
|
u16 rsvd2;
|
||
|
|
u16 rsvd3;
|
||
|
|
u8 src_mac1[6];
|
||
|
|
u16 rsvd4;
|
||
|
|
u8 src_mac0[6];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_smt_write_rpl {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u8 status;
|
||
|
|
u8 rsvd[3];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_smt_read_req {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u8 rsvd0;
|
||
|
|
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
||
|
|
u8 rsvd1:4;
|
||
|
|
u8 iff:4;
|
||
|
|
#else
|
||
|
|
u8 iff:4;
|
||
|
|
u8 rsvd1:4;
|
||
|
|
#endif
|
||
|
|
u16 rsvd2;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_smt_read_rpl {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u8 status;
|
||
|
|
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
||
|
|
u8 rsvd1:1;
|
||
|
|
u8 mtu_idx:3;
|
||
|
|
u8 rsvd0:4;
|
||
|
|
#else
|
||
|
|
u8 rsvd0:4;
|
||
|
|
u8 mtu_idx:3;
|
||
|
|
u8 rsvd1:1;
|
||
|
|
#endif
|
||
|
|
u16 rsvd2;
|
||
|
|
u16 rsvd3;
|
||
|
|
u8 src_mac1[6];
|
||
|
|
u16 rsvd4;
|
||
|
|
u8 src_mac0[6];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_rte_delete_req {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u32 params;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_rte_delete_rpl {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u8 status;
|
||
|
|
u8 rsvd[3];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_rte_write_req {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u32 params;
|
||
|
|
u32 netmask;
|
||
|
|
u32 faddr;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_rte_write_rpl {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u8 status;
|
||
|
|
u8 rsvd[3];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_rte_read_req {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u32 params;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_rte_read_rpl {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u8 status;
|
||
|
|
u8 rsvd0[2];
|
||
|
|
u8 l2t_idx;
|
||
|
|
#if defined(__LITTLE_ENDIAN_BITFIELD)
|
||
|
|
u8 rsvd1:7;
|
||
|
|
u8 select:1;
|
||
|
|
#else
|
||
|
|
u8 select:1;
|
||
|
|
u8 rsvd1:7;
|
||
|
|
#endif
|
||
|
|
u8 rsvd2[3];
|
||
|
|
u32 addr;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct cpl_mss_change {
|
||
|
|
union opcode_tid ot;
|
||
|
|
u32 mss;
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif /* _CXGB_CPL5_CMD_H_ */
|
||
|
|
|