618 lines
16 KiB
C
618 lines
16 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host controller driver for Axis ARTPEC-6 SoC
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*
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* Author: Niklas Cassel <niklas.cassel@axis.com>
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*
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* Based on work done by Phil Edworthy <phil@edworthys.org>
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*/
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/of_device.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include <linux/signal.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/mfd/syscon.h>
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#include <linux/regmap.h>
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#include "pcie-designware.h"
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#define to_artpec6_pcie(x) dev_get_drvdata((x)->dev)
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enum artpec_pcie_variants {
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ARTPEC6,
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ARTPEC7,
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};
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struct artpec6_pcie {
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struct dw_pcie *pci;
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struct regmap *regmap; /* DT axis,syscon-pcie */
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void __iomem *phy_base; /* DT phy */
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enum artpec_pcie_variants variant;
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enum dw_pcie_device_mode mode;
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};
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struct artpec_pcie_of_data {
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enum artpec_pcie_variants variant;
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enum dw_pcie_device_mode mode;
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};
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static const struct of_device_id artpec6_pcie_of_match[];
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/* PCIe Port Logic registers (memory-mapped) */
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#define PL_OFFSET 0x700
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#define ACK_F_ASPM_CTRL_OFF (PL_OFFSET + 0xc)
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#define ACK_N_FTS_MASK GENMASK(15, 8)
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#define ACK_N_FTS(x) (((x) << 8) & ACK_N_FTS_MASK)
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#define FAST_TRAINING_SEQ_MASK GENMASK(7, 0)
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#define FAST_TRAINING_SEQ(x) (((x) << 0) & FAST_TRAINING_SEQ_MASK)
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/* ARTPEC-6 specific registers */
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#define PCIECFG 0x18
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#define PCIECFG_DBG_OEN BIT(24)
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#define PCIECFG_CORE_RESET_REQ BIT(21)
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#define PCIECFG_LTSSM_ENABLE BIT(20)
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#define PCIECFG_DEVICE_TYPE_MASK GENMASK(19, 16)
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#define PCIECFG_CLKREQ_B BIT(11)
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#define PCIECFG_REFCLK_ENABLE BIT(10)
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#define PCIECFG_PLL_ENABLE BIT(9)
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#define PCIECFG_PCLK_ENABLE BIT(8)
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#define PCIECFG_RISRCREN BIT(4)
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#define PCIECFG_MODE_TX_DRV_EN BIT(3)
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#define PCIECFG_CISRREN BIT(2)
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#define PCIECFG_MACRO_ENABLE BIT(0)
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/* ARTPEC-7 specific fields */
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#define PCIECFG_REFCLKSEL BIT(23)
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#define PCIECFG_NOC_RESET BIT(3)
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#define PCIESTAT 0x1c
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/* ARTPEC-7 specific fields */
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#define PCIESTAT_EXTREFCLK BIT(3)
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#define NOCCFG 0x40
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#define NOCCFG_ENABLE_CLK_PCIE BIT(4)
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#define NOCCFG_POWER_PCIE_IDLEACK BIT(3)
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#define NOCCFG_POWER_PCIE_IDLE BIT(2)
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#define NOCCFG_POWER_PCIE_IDLEREQ BIT(1)
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#define PHY_STATUS 0x118
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#define PHY_COSPLLLOCK BIT(0)
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#define PHY_TX_ASIC_OUT 0x4040
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#define PHY_TX_ASIC_OUT_TX_ACK BIT(0)
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#define PHY_RX_ASIC_OUT 0x405c
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#define PHY_RX_ASIC_OUT_ACK BIT(0)
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static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
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{
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u32 val;
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regmap_read(artpec6_pcie->regmap, offset, &val);
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return val;
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}
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static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val)
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{
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regmap_write(artpec6_pcie->regmap, offset, val);
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}
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static u64 artpec6_pcie_cpu_addr_fixup(struct dw_pcie *pci, u64 pci_addr)
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{
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struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
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struct pcie_port *pp = &pci->pp;
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struct dw_pcie_ep *ep = &pci->ep;
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switch (artpec6_pcie->mode) {
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case DW_PCIE_RC_TYPE:
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return pci_addr - pp->cfg0_base;
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case DW_PCIE_EP_TYPE:
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return pci_addr - ep->phys_base;
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default:
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dev_err(pci->dev, "UNKNOWN device type\n");
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}
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return pci_addr;
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}
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static int artpec6_pcie_establish_link(struct dw_pcie *pci)
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{
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struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
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u32 val;
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val |= PCIECFG_LTSSM_ENABLE;
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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return 0;
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}
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static void artpec6_pcie_stop_link(struct dw_pcie *pci)
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{
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struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
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u32 val;
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val &= ~PCIECFG_LTSSM_ENABLE;
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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}
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static const struct dw_pcie_ops dw_pcie_ops = {
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.cpu_addr_fixup = artpec6_pcie_cpu_addr_fixup,
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.start_link = artpec6_pcie_establish_link,
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.stop_link = artpec6_pcie_stop_link,
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};
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static void artpec6_pcie_wait_for_phy_a6(struct artpec6_pcie *artpec6_pcie)
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{
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struct dw_pcie *pci = artpec6_pcie->pci;
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struct device *dev = pci->dev;
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u32 val;
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unsigned int retries;
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retries = 50;
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do {
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usleep_range(1000, 2000);
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val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
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retries--;
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} while (retries &&
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(val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
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if (!retries)
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dev_err(dev, "PCIe clock manager did not leave idle state\n");
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retries = 50;
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do {
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usleep_range(1000, 2000);
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val = readl(artpec6_pcie->phy_base + PHY_STATUS);
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retries--;
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} while (retries && !(val & PHY_COSPLLLOCK));
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if (!retries)
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dev_err(dev, "PHY PLL did not lock\n");
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}
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static void artpec6_pcie_wait_for_phy_a7(struct artpec6_pcie *artpec6_pcie)
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{
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struct dw_pcie *pci = artpec6_pcie->pci;
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struct device *dev = pci->dev;
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u32 val;
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u16 phy_status_tx, phy_status_rx;
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unsigned int retries;
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retries = 50;
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do {
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usleep_range(1000, 2000);
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val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
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retries--;
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} while (retries &&
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(val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
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if (!retries)
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dev_err(dev, "PCIe clock manager did not leave idle state\n");
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retries = 50;
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do {
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usleep_range(1000, 2000);
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phy_status_tx = readw(artpec6_pcie->phy_base + PHY_TX_ASIC_OUT);
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phy_status_rx = readw(artpec6_pcie->phy_base + PHY_RX_ASIC_OUT);
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retries--;
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} while (retries && ((phy_status_tx & PHY_TX_ASIC_OUT_TX_ACK) ||
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(phy_status_rx & PHY_RX_ASIC_OUT_ACK)));
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if (!retries)
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dev_err(dev, "PHY did not enter Pn state\n");
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}
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static void artpec6_pcie_wait_for_phy(struct artpec6_pcie *artpec6_pcie)
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{
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switch (artpec6_pcie->variant) {
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case ARTPEC6:
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artpec6_pcie_wait_for_phy_a6(artpec6_pcie);
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break;
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case ARTPEC7:
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artpec6_pcie_wait_for_phy_a7(artpec6_pcie);
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break;
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}
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}
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static void artpec6_pcie_init_phy_a6(struct artpec6_pcie *artpec6_pcie)
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{
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u32 val;
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */
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PCIECFG_MODE_TX_DRV_EN |
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PCIECFG_CISRREN | /* Reference clock term. 100 Ohm */
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PCIECFG_MACRO_ENABLE;
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val |= PCIECFG_REFCLK_ENABLE;
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val &= ~PCIECFG_DBG_OEN;
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val &= ~PCIECFG_CLKREQ_B;
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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usleep_range(5000, 6000);
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val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
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val |= NOCCFG_ENABLE_CLK_PCIE;
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artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
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usleep_range(20, 30);
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE;
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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usleep_range(6000, 7000);
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val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
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val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
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artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
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}
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static void artpec6_pcie_init_phy_a7(struct artpec6_pcie *artpec6_pcie)
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{
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struct dw_pcie *pci = artpec6_pcie->pci;
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u32 val;
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bool extrefclk;
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/* Check if external reference clock is connected */
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val = artpec6_pcie_readl(artpec6_pcie, PCIESTAT);
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extrefclk = !!(val & PCIESTAT_EXTREFCLK);
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dev_dbg(pci->dev, "Using reference clock: %s\n",
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extrefclk ? "external" : "internal");
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */
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PCIECFG_PCLK_ENABLE;
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if (extrefclk)
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val |= PCIECFG_REFCLKSEL;
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else
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val &= ~PCIECFG_REFCLKSEL;
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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usleep_range(10, 20);
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val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
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val |= NOCCFG_ENABLE_CLK_PCIE;
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artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
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usleep_range(20, 30);
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val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
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val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
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artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
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}
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static void artpec6_pcie_init_phy(struct artpec6_pcie *artpec6_pcie)
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{
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switch (artpec6_pcie->variant) {
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case ARTPEC6:
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artpec6_pcie_init_phy_a6(artpec6_pcie);
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break;
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case ARTPEC7:
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artpec6_pcie_init_phy_a7(artpec6_pcie);
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break;
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}
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}
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static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)
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{
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struct dw_pcie *pci = artpec6_pcie->pci;
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u32 val;
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if (artpec6_pcie->variant != ARTPEC7)
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return;
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/*
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* Increase the N_FTS (Number of Fast Training Sequences)
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* to be transmitted when transitioning from L0s to L0.
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*/
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val = dw_pcie_readl_dbi(pci, ACK_F_ASPM_CTRL_OFF);
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val &= ~ACK_N_FTS_MASK;
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val |= ACK_N_FTS(180);
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dw_pcie_writel_dbi(pci, ACK_F_ASPM_CTRL_OFF, val);
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/*
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* Set the Number of Fast Training Sequences that the core
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* advertises as its N_FTS during Gen2 or Gen3 link training.
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*/
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val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
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val &= ~FAST_TRAINING_SEQ_MASK;
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val |= FAST_TRAINING_SEQ(180);
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dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
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}
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static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
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{
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u32 val;
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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switch (artpec6_pcie->variant) {
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case ARTPEC6:
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val |= PCIECFG_CORE_RESET_REQ;
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break;
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case ARTPEC7:
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val &= ~PCIECFG_NOC_RESET;
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break;
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}
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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}
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static void artpec6_pcie_deassert_core_reset(struct artpec6_pcie *artpec6_pcie)
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||
|
|
{
|
||
|
|
u32 val;
|
||
|
|
|
||
|
|
val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
|
||
|
|
switch (artpec6_pcie->variant) {
|
||
|
|
case ARTPEC6:
|
||
|
|
val &= ~PCIECFG_CORE_RESET_REQ;
|
||
|
|
break;
|
||
|
|
case ARTPEC7:
|
||
|
|
val |= PCIECFG_NOC_RESET;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
|
||
|
|
usleep_range(100, 200);
|
||
|
|
}
|
||
|
|
|
||
|
|
static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
|
||
|
|
{
|
||
|
|
struct dw_pcie *pci = artpec6_pcie->pci;
|
||
|
|
struct pcie_port *pp = &pci->pp;
|
||
|
|
|
||
|
|
if (IS_ENABLED(CONFIG_PCI_MSI))
|
||
|
|
dw_pcie_msi_init(pp);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int artpec6_pcie_host_init(struct pcie_port *pp)
|
||
|
|
{
|
||
|
|
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
|
||
|
|
struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
|
||
|
|
|
||
|
|
artpec6_pcie_assert_core_reset(artpec6_pcie);
|
||
|
|
artpec6_pcie_init_phy(artpec6_pcie);
|
||
|
|
artpec6_pcie_deassert_core_reset(artpec6_pcie);
|
||
|
|
artpec6_pcie_wait_for_phy(artpec6_pcie);
|
||
|
|
artpec6_pcie_set_nfts(artpec6_pcie);
|
||
|
|
dw_pcie_setup_rc(pp);
|
||
|
|
artpec6_pcie_establish_link(pci);
|
||
|
|
dw_pcie_wait_for_link(pci);
|
||
|
|
artpec6_pcie_enable_interrupts(artpec6_pcie);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct dw_pcie_host_ops artpec6_pcie_host_ops = {
|
||
|
|
.host_init = artpec6_pcie_host_init,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
|
||
|
|
struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct dw_pcie *pci = artpec6_pcie->pci;
|
||
|
|
struct pcie_port *pp = &pci->pp;
|
||
|
|
struct device *dev = pci->dev;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||
|
|
pp->msi_irq = platform_get_irq_byname(pdev, "msi");
|
||
|
|
if (pp->msi_irq < 0) {
|
||
|
|
dev_err(dev, "failed to get MSI irq\n");
|
||
|
|
return pp->msi_irq;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
pp->ops = &artpec6_pcie_host_ops;
|
||
|
|
|
||
|
|
ret = dw_pcie_host_init(pp);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(dev, "failed to initialize host\n");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
|
||
|
|
{
|
||
|
|
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||
|
|
struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
|
||
|
|
enum pci_barno bar;
|
||
|
|
|
||
|
|
artpec6_pcie_assert_core_reset(artpec6_pcie);
|
||
|
|
artpec6_pcie_init_phy(artpec6_pcie);
|
||
|
|
artpec6_pcie_deassert_core_reset(artpec6_pcie);
|
||
|
|
artpec6_pcie_wait_for_phy(artpec6_pcie);
|
||
|
|
artpec6_pcie_set_nfts(artpec6_pcie);
|
||
|
|
|
||
|
|
for (bar = BAR_0; bar <= BAR_5; bar++)
|
||
|
|
dw_pcie_ep_reset_bar(pci, bar);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
|
||
|
|
enum pci_epc_irq_type type, u16 interrupt_num)
|
||
|
|
{
|
||
|
|
struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
|
||
|
|
|
||
|
|
switch (type) {
|
||
|
|
case PCI_EPC_IRQ_LEGACY:
|
||
|
|
dev_err(pci->dev, "EP cannot trigger legacy IRQs\n");
|
||
|
|
return -EINVAL;
|
||
|
|
case PCI_EPC_IRQ_MSI:
|
||
|
|
return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
|
||
|
|
default:
|
||
|
|
dev_err(pci->dev, "UNKNOWN IRQ type\n");
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct dw_pcie_ep_ops pcie_ep_ops = {
|
||
|
|
.ep_init = artpec6_pcie_ep_init,
|
||
|
|
.raise_irq = artpec6_pcie_raise_irq,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int artpec6_add_pcie_ep(struct artpec6_pcie *artpec6_pcie,
|
||
|
|
struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
int ret;
|
||
|
|
struct dw_pcie_ep *ep;
|
||
|
|
struct resource *res;
|
||
|
|
struct device *dev = &pdev->dev;
|
||
|
|
struct dw_pcie *pci = artpec6_pcie->pci;
|
||
|
|
|
||
|
|
ep = &pci->ep;
|
||
|
|
ep->ops = &pcie_ep_ops;
|
||
|
|
|
||
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2");
|
||
|
|
pci->dbi_base2 = devm_ioremap_resource(dev, res);
|
||
|
|
if (IS_ERR(pci->dbi_base2))
|
||
|
|
return PTR_ERR(pci->dbi_base2);
|
||
|
|
|
||
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
|
||
|
|
if (!res)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
ep->phys_base = res->start;
|
||
|
|
ep->addr_size = resource_size(res);
|
||
|
|
|
||
|
|
ret = dw_pcie_ep_init(ep);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(dev, "failed to initialize endpoint\n");
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int artpec6_pcie_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct device *dev = &pdev->dev;
|
||
|
|
struct dw_pcie *pci;
|
||
|
|
struct artpec6_pcie *artpec6_pcie;
|
||
|
|
struct resource *dbi_base;
|
||
|
|
struct resource *phy_base;
|
||
|
|
int ret;
|
||
|
|
const struct of_device_id *match;
|
||
|
|
const struct artpec_pcie_of_data *data;
|
||
|
|
enum artpec_pcie_variants variant;
|
||
|
|
enum dw_pcie_device_mode mode;
|
||
|
|
|
||
|
|
match = of_match_device(artpec6_pcie_of_match, dev);
|
||
|
|
if (!match)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
data = (struct artpec_pcie_of_data *)match->data;
|
||
|
|
variant = (enum artpec_pcie_variants)data->variant;
|
||
|
|
mode = (enum dw_pcie_device_mode)data->mode;
|
||
|
|
|
||
|
|
artpec6_pcie = devm_kzalloc(dev, sizeof(*artpec6_pcie), GFP_KERNEL);
|
||
|
|
if (!artpec6_pcie)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
|
||
|
|
if (!pci)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
pci->dev = dev;
|
||
|
|
pci->ops = &dw_pcie_ops;
|
||
|
|
|
||
|
|
artpec6_pcie->pci = pci;
|
||
|
|
artpec6_pcie->variant = variant;
|
||
|
|
artpec6_pcie->mode = mode;
|
||
|
|
|
||
|
|
dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
|
||
|
|
pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
|
||
|
|
if (IS_ERR(pci->dbi_base))
|
||
|
|
return PTR_ERR(pci->dbi_base);
|
||
|
|
|
||
|
|
phy_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
|
||
|
|
artpec6_pcie->phy_base = devm_ioremap_resource(dev, phy_base);
|
||
|
|
if (IS_ERR(artpec6_pcie->phy_base))
|
||
|
|
return PTR_ERR(artpec6_pcie->phy_base);
|
||
|
|
|
||
|
|
artpec6_pcie->regmap =
|
||
|
|
syscon_regmap_lookup_by_phandle(dev->of_node,
|
||
|
|
"axis,syscon-pcie");
|
||
|
|
if (IS_ERR(artpec6_pcie->regmap))
|
||
|
|
return PTR_ERR(artpec6_pcie->regmap);
|
||
|
|
|
||
|
|
platform_set_drvdata(pdev, artpec6_pcie);
|
||
|
|
|
||
|
|
switch (artpec6_pcie->mode) {
|
||
|
|
case DW_PCIE_RC_TYPE:
|
||
|
|
if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_HOST))
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
ret = artpec6_add_pcie_port(artpec6_pcie, pdev);
|
||
|
|
if (ret < 0)
|
||
|
|
return ret;
|
||
|
|
break;
|
||
|
|
case DW_PCIE_EP_TYPE: {
|
||
|
|
u32 val;
|
||
|
|
|
||
|
|
if (!IS_ENABLED(CONFIG_PCIE_ARTPEC6_EP))
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
|
||
|
|
val &= ~PCIECFG_DEVICE_TYPE_MASK;
|
||
|
|
artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
|
||
|
|
ret = artpec6_add_pcie_ep(artpec6_pcie, pdev);
|
||
|
|
if (ret < 0)
|
||
|
|
return ret;
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
default:
|
||
|
|
dev_err(dev, "INVALID device type %d\n", artpec6_pcie->mode);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct artpec_pcie_of_data artpec6_pcie_rc_of_data = {
|
||
|
|
.variant = ARTPEC6,
|
||
|
|
.mode = DW_PCIE_RC_TYPE,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct artpec_pcie_of_data artpec6_pcie_ep_of_data = {
|
||
|
|
.variant = ARTPEC6,
|
||
|
|
.mode = DW_PCIE_EP_TYPE,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct artpec_pcie_of_data artpec7_pcie_rc_of_data = {
|
||
|
|
.variant = ARTPEC7,
|
||
|
|
.mode = DW_PCIE_RC_TYPE,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct artpec_pcie_of_data artpec7_pcie_ep_of_data = {
|
||
|
|
.variant = ARTPEC7,
|
||
|
|
.mode = DW_PCIE_EP_TYPE,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id artpec6_pcie_of_match[] = {
|
||
|
|
{
|
||
|
|
.compatible = "axis,artpec6-pcie",
|
||
|
|
.data = &artpec6_pcie_rc_of_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "axis,artpec6-pcie-ep",
|
||
|
|
.data = &artpec6_pcie_ep_of_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "axis,artpec7-pcie",
|
||
|
|
.data = &artpec7_pcie_rc_of_data,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.compatible = "axis,artpec7-pcie-ep",
|
||
|
|
.data = &artpec7_pcie_ep_of_data,
|
||
|
|
},
|
||
|
|
{},
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_driver artpec6_pcie_driver = {
|
||
|
|
.probe = artpec6_pcie_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "artpec6-pcie",
|
||
|
|
.of_match_table = artpec6_pcie_of_match,
|
||
|
|
.suppress_bind_attrs = true,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
builtin_platform_driver(artpec6_pcie_driver);
|