358 lines
13 KiB
C
358 lines
13 KiB
C
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/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _DT_BINDINGS_CLK_APQ_GCC_8084_H
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#define _DT_BINDINGS_CLK_APQ_GCC_8084_H
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#define GPLL0 0
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#define GPLL0_VOTE 1
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#define GPLL1 2
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#define GPLL1_VOTE 3
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#define GPLL2 4
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#define GPLL2_VOTE 5
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#define GPLL3 6
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#define GPLL3_VOTE 7
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#define GPLL4 8
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#define GPLL4_VOTE 9
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#define CONFIG_NOC_CLK_SRC 10
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#define PERIPH_NOC_CLK_SRC 11
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#define SYSTEM_NOC_CLK_SRC 12
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#define BLSP_UART_SIM_CLK_SRC 13
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#define QDSS_TSCTR_CLK_SRC 14
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#define UFS_AXI_CLK_SRC 15
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#define RPM_CLK_SRC 16
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#define KPSS_AHB_CLK_SRC 17
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#define QDSS_AT_CLK_SRC 18
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#define BIMC_DDR_CLK_SRC 19
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#define USB30_MASTER_CLK_SRC 20
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#define USB30_SEC_MASTER_CLK_SRC 21
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#define USB_HSIC_AHB_CLK_SRC 22
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#define MMSS_BIMC_GFX_CLK_SRC 23
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#define QDSS_STM_CLK_SRC 24
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#define ACC_CLK_SRC 25
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#define SEC_CTRL_CLK_SRC 26
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#define BLSP1_QUP1_I2C_APPS_CLK_SRC 27
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#define BLSP1_QUP1_SPI_APPS_CLK_SRC 28
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#define BLSP1_QUP2_I2C_APPS_CLK_SRC 29
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#define BLSP1_QUP2_SPI_APPS_CLK_SRC 30
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#define BLSP1_QUP3_I2C_APPS_CLK_SRC 31
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#define BLSP1_QUP3_SPI_APPS_CLK_SRC 32
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#define BLSP1_QUP4_I2C_APPS_CLK_SRC 33
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#define BLSP1_QUP4_SPI_APPS_CLK_SRC 34
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#define BLSP1_QUP5_I2C_APPS_CLK_SRC 35
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#define BLSP1_QUP5_SPI_APPS_CLK_SRC 36
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#define BLSP1_QUP6_I2C_APPS_CLK_SRC 37
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#define BLSP1_QUP6_SPI_APPS_CLK_SRC 38
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#define BLSP1_UART1_APPS_CLK_SRC 39
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#define BLSP1_UART2_APPS_CLK_SRC 40
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#define BLSP1_UART3_APPS_CLK_SRC 41
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#define BLSP1_UART4_APPS_CLK_SRC 42
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#define BLSP1_UART5_APPS_CLK_SRC 43
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#define BLSP1_UART6_APPS_CLK_SRC 44
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#define BLSP2_QUP1_I2C_APPS_CLK_SRC 45
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#define BLSP2_QUP1_SPI_APPS_CLK_SRC 46
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#define BLSP2_QUP2_I2C_APPS_CLK_SRC 47
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#define BLSP2_QUP2_SPI_APPS_CLK_SRC 48
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#define BLSP2_QUP3_I2C_APPS_CLK_SRC 49
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#define BLSP2_QUP3_SPI_APPS_CLK_SRC 50
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#define BLSP2_QUP4_I2C_APPS_CLK_SRC 51
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#define BLSP2_QUP4_SPI_APPS_CLK_SRC 52
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#define BLSP2_QUP5_I2C_APPS_CLK_SRC 53
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#define BLSP2_QUP5_SPI_APPS_CLK_SRC 54
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#define BLSP2_QUP6_I2C_APPS_CLK_SRC 55
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#define BLSP2_QUP6_SPI_APPS_CLK_SRC 56
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#define BLSP2_UART1_APPS_CLK_SRC 57
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#define BLSP2_UART2_APPS_CLK_SRC 58
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#define BLSP2_UART3_APPS_CLK_SRC 59
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#define BLSP2_UART4_APPS_CLK_SRC 60
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#define BLSP2_UART5_APPS_CLK_SRC 61
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#define BLSP2_UART6_APPS_CLK_SRC 62
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#define CE1_CLK_SRC 63
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#define CE2_CLK_SRC 64
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#define CE3_CLK_SRC 65
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#define GP1_CLK_SRC 66
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#define GP2_CLK_SRC 67
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#define GP3_CLK_SRC 68
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#define PDM2_CLK_SRC 69
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#define QDSS_TRACECLKIN_CLK_SRC 70
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#define RBCPR_CLK_SRC 71
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#define SATA_ASIC0_CLK_SRC 72
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#define SATA_PMALIVE_CLK_SRC 73
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#define SATA_RX_CLK_SRC 74
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#define SATA_RX_OOB_CLK_SRC 75
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#define SDCC1_APPS_CLK_SRC 76
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#define SDCC2_APPS_CLK_SRC 77
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#define SDCC3_APPS_CLK_SRC 78
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#define SDCC4_APPS_CLK_SRC 79
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#define GCC_SNOC_BUS_TIMEOUT0_AHB_CLK 80
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#define SPMI_AHB_CLK_SRC 81
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#define SPMI_SER_CLK_SRC 82
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#define TSIF_REF_CLK_SRC 83
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#define USB30_MOCK_UTMI_CLK_SRC 84
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#define USB30_SEC_MOCK_UTMI_CLK_SRC 85
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#define USB_HS_SYSTEM_CLK_SRC 86
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#define USB_HSIC_CLK_SRC 87
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#define USB_HSIC_IO_CAL_CLK_SRC 88
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#define USB_HSIC_MOCK_UTMI_CLK_SRC 89
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#define USB_HSIC_SYSTEM_CLK_SRC 90
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#define GCC_BAM_DMA_AHB_CLK 91
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#define GCC_BAM_DMA_INACTIVITY_TIMERS_CLK 92
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#define DDR_CLK_SRC 93
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#define GCC_BIMC_CFG_AHB_CLK 94
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#define GCC_BIMC_CLK 95
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#define GCC_BIMC_KPSS_AXI_CLK 96
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#define GCC_BIMC_SLEEP_CLK 97
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#define GCC_BIMC_SYSNOC_AXI_CLK 98
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#define GCC_BIMC_XO_CLK 99
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#define GCC_BLSP1_AHB_CLK 100
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#define GCC_BLSP1_SLEEP_CLK 101
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#define GCC_BLSP1_QUP1_I2C_APPS_CLK 102
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#define GCC_BLSP1_QUP1_SPI_APPS_CLK 103
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#define GCC_BLSP1_QUP2_I2C_APPS_CLK 104
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#define GCC_BLSP1_QUP2_SPI_APPS_CLK 105
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#define GCC_BLSP1_QUP3_I2C_APPS_CLK 106
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#define GCC_BLSP1_QUP3_SPI_APPS_CLK 107
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#define GCC_BLSP1_QUP4_I2C_APPS_CLK 108
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#define GCC_BLSP1_QUP4_SPI_APPS_CLK 109
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#define GCC_BLSP1_QUP5_I2C_APPS_CLK 110
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#define GCC_BLSP1_QUP5_SPI_APPS_CLK 111
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#define GCC_BLSP1_QUP6_I2C_APPS_CLK 112
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#define GCC_BLSP1_QUP6_SPI_APPS_CLK 113
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#define GCC_BLSP1_UART1_APPS_CLK 114
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#define GCC_BLSP1_UART1_SIM_CLK 115
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#define GCC_BLSP1_UART2_APPS_CLK 116
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#define GCC_BLSP1_UART2_SIM_CLK 117
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#define GCC_BLSP1_UART3_APPS_CLK 118
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#define GCC_BLSP1_UART3_SIM_CLK 119
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#define GCC_BLSP1_UART4_APPS_CLK 120
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#define GCC_BLSP1_UART4_SIM_CLK 121
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#define GCC_BLSP1_UART5_APPS_CLK 122
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#define GCC_BLSP1_UART5_SIM_CLK 123
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#define GCC_BLSP1_UART6_APPS_CLK 124
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#define GCC_BLSP1_UART6_SIM_CLK 125
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#define GCC_BLSP2_AHB_CLK 126
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#define GCC_BLSP2_SLEEP_CLK 127
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#define GCC_BLSP2_QUP1_I2C_APPS_CLK 128
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#define GCC_BLSP2_QUP1_SPI_APPS_CLK 129
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#define GCC_BLSP2_QUP2_I2C_APPS_CLK 130
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#define GCC_BLSP2_QUP2_SPI_APPS_CLK 131
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#define GCC_BLSP2_QUP3_I2C_APPS_CLK 132
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#define GCC_BLSP2_QUP3_SPI_APPS_CLK 133
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#define GCC_BLSP2_QUP4_I2C_APPS_CLK 134
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#define GCC_BLSP2_QUP4_SPI_APPS_CLK 135
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#define GCC_BLSP2_QUP5_I2C_APPS_CLK 136
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#define GCC_BLSP2_QUP5_SPI_APPS_CLK 137
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#define GCC_BLSP2_QUP6_I2C_APPS_CLK 138
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#define GCC_BLSP2_QUP6_SPI_APPS_CLK 139
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#define GCC_BLSP2_UART1_APPS_CLK 140
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#define GCC_BLSP2_UART1_SIM_CLK 141
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#define GCC_BLSP2_UART2_APPS_CLK 142
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#define GCC_BLSP2_UART2_SIM_CLK 143
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#define GCC_BLSP2_UART3_APPS_CLK 144
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#define GCC_BLSP2_UART3_SIM_CLK 145
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#define GCC_BLSP2_UART4_APPS_CLK 146
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#define GCC_BLSP2_UART4_SIM_CLK 147
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#define GCC_BLSP2_UART5_APPS_CLK 148
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#define GCC_BLSP2_UART5_SIM_CLK 149
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#define GCC_BLSP2_UART6_APPS_CLK 150
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#define GCC_BLSP2_UART6_SIM_CLK 151
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#define GCC_BOOT_ROM_AHB_CLK 152
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#define GCC_CE1_AHB_CLK 153
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#define GCC_CE1_AXI_CLK 154
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#define GCC_CE1_CLK 155
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#define GCC_CE2_AHB_CLK 156
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#define GCC_CE2_AXI_CLK 157
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#define GCC_CE2_CLK 158
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#define GCC_CE3_AHB_CLK 159
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#define GCC_CE3_AXI_CLK 160
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#define GCC_CE3_CLK 161
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#define GCC_CNOC_BUS_TIMEOUT0_AHB_CLK 162
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#define GCC_CNOC_BUS_TIMEOUT1_AHB_CLK 163
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#define GCC_CNOC_BUS_TIMEOUT2_AHB_CLK 164
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#define GCC_CNOC_BUS_TIMEOUT3_AHB_CLK 165
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#define GCC_CNOC_BUS_TIMEOUT4_AHB_CLK 166
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#define GCC_CNOC_BUS_TIMEOUT5_AHB_CLK 167
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#define GCC_CNOC_BUS_TIMEOUT6_AHB_CLK 168
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#define GCC_CNOC_BUS_TIMEOUT7_AHB_CLK 169
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#define GCC_CFG_NOC_AHB_CLK 170
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#define GCC_CFG_NOC_DDR_CFG_CLK 171
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#define GCC_CFG_NOC_RPM_AHB_CLK 172
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#define GCC_COPSS_SMMU_AHB_CLK 173
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#define GCC_COPSS_SMMU_AXI_CLK 174
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#define GCC_DCD_XO_CLK 175
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#define GCC_BIMC_DDR_CH0_CLK 176
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#define GCC_BIMC_DDR_CH1_CLK 177
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#define GCC_BIMC_DDR_CPLL0_CLK 178
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#define GCC_BIMC_DDR_CPLL1_CLK 179
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#define GCC_BIMC_GFX_CLK 180
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#define GCC_DDR_DIM_CFG_CLK 181
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#define GCC_DDR_DIM_SLEEP_CLK 182
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#define GCC_DEHR_CLK 183
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#define GCC_AHB_CLK 184
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#define GCC_IM_SLEEP_CLK 185
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#define GCC_XO_CLK 186
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#define GCC_XO_DIV4_CLK 187
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#define GCC_GP1_CLK 188
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#define GCC_GP2_CLK 189
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#define GCC_GP3_CLK 190
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#define GCC_IMEM_AXI_CLK 191
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#define GCC_IMEM_CFG_AHB_CLK 192
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#define GCC_KPSS_AHB_CLK 193
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#define GCC_KPSS_AXI_CLK 194
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#define GCC_LPASS_MPORT_AXI_CLK 195
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#define GCC_LPASS_Q6_AXI_CLK 196
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#define GCC_LPASS_SWAY_CLK 197
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#define GCC_MMSS_BIMC_GFX_CLK 198
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#define GCC_MMSS_NOC_AT_CLK 199
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#define GCC_MMSS_NOC_CFG_AHB_CLK 200
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#define GCC_MMSS_VPU_MAPLE_SYS_NOC_AXI_CLK 201
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#define GCC_OCMEM_NOC_CFG_AHB_CLK 202
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#define GCC_OCMEM_SYS_NOC_AXI_CLK 203
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#define GCC_MPM_AHB_CLK 204
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#define GCC_MSG_RAM_AHB_CLK 205
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#define GCC_NOC_CONF_XPU_AHB_CLK 206
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#define GCC_PDM2_CLK 207
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#define GCC_PDM_AHB_CLK 208
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#define GCC_PDM_XO4_CLK 209
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#define GCC_PERIPH_NOC_AHB_CLK 210
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#define GCC_PERIPH_NOC_AT_CLK 211
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#define GCC_PERIPH_NOC_CFG_AHB_CLK 212
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#define GCC_PERIPH_NOC_USB_HSIC_AHB_CLK 213
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#define GCC_PERIPH_NOC_MPU_CFG_AHB_CLK 214
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#define GCC_PERIPH_XPU_AHB_CLK 215
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#define GCC_PNOC_BUS_TIMEOUT0_AHB_CLK 216
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#define GCC_PNOC_BUS_TIMEOUT1_AHB_CLK 217
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#define GCC_PNOC_BUS_TIMEOUT2_AHB_CLK 218
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#define GCC_PNOC_BUS_TIMEOUT3_AHB_CLK 219
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#define GCC_PNOC_BUS_TIMEOUT4_AHB_CLK 220
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#define GCC_PRNG_AHB_CLK 221
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#define GCC_QDSS_AT_CLK 222
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#define GCC_QDSS_CFG_AHB_CLK 223
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#define GCC_QDSS_DAP_AHB_CLK 224
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#define GCC_QDSS_DAP_CLK 225
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#define GCC_QDSS_ETR_USB_CLK 226
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#define GCC_QDSS_STM_CLK 227
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#define GCC_QDSS_TRACECLKIN_CLK 228
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#define GCC_QDSS_TSCTR_DIV16_CLK 229
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#define GCC_QDSS_TSCTR_DIV2_CLK 230
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#define GCC_QDSS_TSCTR_DIV3_CLK 231
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#define GCC_QDSS_TSCTR_DIV4_CLK 232
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#define GCC_QDSS_TSCTR_DIV8_CLK 233
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#define GCC_QDSS_RBCPR_XPU_AHB_CLK 234
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#define GCC_RBCPR_AHB_CLK 235
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#define GCC_RBCPR_CLK 236
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#define GCC_RPM_BUS_AHB_CLK 237
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#define GCC_RPM_PROC_HCLK 238
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#define GCC_RPM_SLEEP_CLK 239
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#define GCC_RPM_TIMER_CLK 240
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#define GCC_SATA_ASIC0_CLK 241
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#define GCC_SATA_AXI_CLK 242
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#define GCC_SATA_CFG_AHB_CLK 243
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#define GCC_SATA_PMALIVE_CLK 244
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#define GCC_SATA_RX_CLK 245
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#define GCC_SATA_RX_OOB_CLK 246
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#define GCC_SDCC1_AHB_CLK 247
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#define GCC_SDCC1_APPS_CLK 248
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#define GCC_SDCC1_CDCCAL_FF_CLK 249
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#define GCC_SDCC1_CDCCAL_SLEEP_CLK 250
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#define GCC_SDCC2_AHB_CLK 251
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#define GCC_SDCC2_APPS_CLK 252
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#define GCC_SDCC2_INACTIVITY_TIMERS_CLK 253
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#define GCC_SDCC3_AHB_CLK 254
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#define GCC_SDCC3_APPS_CLK 255
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#define GCC_SDCC3_INACTIVITY_TIMERS_CLK 256
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#define GCC_SDCC4_AHB_CLK 257
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#define GCC_SDCC4_APPS_CLK 258
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#define GCC_SDCC4_INACTIVITY_TIMERS_CLK 259
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#define GCC_SEC_CTRL_ACC_CLK 260
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#define GCC_SEC_CTRL_AHB_CLK 261
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#define GCC_SEC_CTRL_BOOT_ROM_PATCH_CLK 262
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#define GCC_SEC_CTRL_CLK 263
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#define GCC_SEC_CTRL_SENSE_CLK 264
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#define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK 265
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#define GCC_SNOC_BUS_TIMEOUT3_AHB_CLK 266
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#define GCC_SPDM_BIMC_CY_CLK 267
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#define GCC_SPDM_CFG_AHB_CLK 268
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#define GCC_SPDM_DEBUG_CY_CLK 269
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||
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#define GCC_SPDM_FF_CLK 270
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||
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#define GCC_SPDM_MSTR_AHB_CLK 271
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||
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#define GCC_SPDM_PNOC_CY_CLK 272
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||
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#define GCC_SPDM_RPM_CY_CLK 273
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||
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#define GCC_SPDM_SNOC_CY_CLK 274
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||
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#define GCC_SPMI_AHB_CLK 275
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||
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#define GCC_SPMI_CNOC_AHB_CLK 276
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||
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#define GCC_SPMI_SER_CLK 277
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||
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#define GCC_SPSS_AHB_CLK 278
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||
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#define GCC_SNOC_CNOC_AHB_CLK 279
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||
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#define GCC_SNOC_PNOC_AHB_CLK 280
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||
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#define GCC_SYS_NOC_AT_CLK 281
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||
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#define GCC_SYS_NOC_AXI_CLK 282
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||
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#define GCC_SYS_NOC_KPSS_AHB_CLK 283
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||
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#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 284
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||
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#define GCC_SYS_NOC_UFS_AXI_CLK 285
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||
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|
#define GCC_SYS_NOC_USB3_AXI_CLK 286
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||
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|
#define GCC_SYS_NOC_USB3_SEC_AXI_CLK 287
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||
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|
#define GCC_TCSR_AHB_CLK 288
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||
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|
#define GCC_TLMM_AHB_CLK 289
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||
|
|
#define GCC_TLMM_CLK 290
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||
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|
#define GCC_TSIF_AHB_CLK 291
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||
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|
#define GCC_TSIF_INACTIVITY_TIMERS_CLK 292
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||
|
|
#define GCC_TSIF_REF_CLK 293
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||
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|
#define GCC_UFS_AHB_CLK 294
|
||
|
|
#define GCC_UFS_AXI_CLK 295
|
||
|
|
#define GCC_UFS_RX_CFG_CLK 296
|
||
|
|
#define GCC_UFS_RX_SYMBOL_0_CLK 297
|
||
|
|
#define GCC_UFS_RX_SYMBOL_1_CLK 298
|
||
|
|
#define GCC_UFS_TX_CFG_CLK 299
|
||
|
|
#define GCC_UFS_TX_SYMBOL_0_CLK 300
|
||
|
|
#define GCC_UFS_TX_SYMBOL_1_CLK 301
|
||
|
|
#define GCC_USB2A_PHY_SLEEP_CLK 302
|
||
|
|
#define GCC_USB2B_PHY_SLEEP_CLK 303
|
||
|
|
#define GCC_USB30_MASTER_CLK 304
|
||
|
|
#define GCC_USB30_MOCK_UTMI_CLK 305
|
||
|
|
#define GCC_USB30_SLEEP_CLK 306
|
||
|
|
#define GCC_USB30_SEC_MASTER_CLK 307
|
||
|
|
#define GCC_USB30_SEC_MOCK_UTMI_CLK 308
|
||
|
|
#define GCC_USB30_SEC_SLEEP_CLK 309
|
||
|
|
#define GCC_USB_HS_AHB_CLK 310
|
||
|
|
#define GCC_USB_HS_INACTIVITY_TIMERS_CLK 311
|
||
|
|
#define GCC_USB_HS_SYSTEM_CLK 312
|
||
|
|
#define GCC_USB_HSIC_AHB_CLK 313
|
||
|
|
#define GCC_USB_HSIC_CLK 314
|
||
|
|
#define GCC_USB_HSIC_IO_CAL_CLK 315
|
||
|
|
#define GCC_USB_HSIC_IO_CAL_SLEEP_CLK 316
|
||
|
|
#define GCC_USB_HSIC_MOCK_UTMI_CLK 317
|
||
|
|
#define GCC_USB_HSIC_SYSTEM_CLK 318
|
||
|
|
#define PCIE_0_AUX_CLK_SRC 319
|
||
|
|
#define PCIE_0_PIPE_CLK_SRC 320
|
||
|
|
#define PCIE_1_AUX_CLK_SRC 321
|
||
|
|
#define PCIE_1_PIPE_CLK_SRC 322
|
||
|
|
#define GCC_PCIE_0_AUX_CLK 323
|
||
|
|
#define GCC_PCIE_0_CFG_AHB_CLK 324
|
||
|
|
#define GCC_PCIE_0_MSTR_AXI_CLK 325
|
||
|
|
#define GCC_PCIE_0_PIPE_CLK 326
|
||
|
|
#define GCC_PCIE_0_SLV_AXI_CLK 327
|
||
|
|
#define GCC_PCIE_1_AUX_CLK 328
|
||
|
|
#define GCC_PCIE_1_CFG_AHB_CLK 329
|
||
|
|
#define GCC_PCIE_1_MSTR_AXI_CLK 330
|
||
|
|
#define GCC_PCIE_1_PIPE_CLK 331
|
||
|
|
#define GCC_PCIE_1_SLV_AXI_CLK 332
|
||
|
|
|
||
|
|
/* gdscs */
|
||
|
|
#define USB_HS_HSIC_GDSC 0
|
||
|
|
#define PCIE0_GDSC 1
|
||
|
|
#define PCIE1_GDSC 2
|
||
|
|
#define USB30_GDSC 3
|
||
|
|
|
||
|
|
#endif
|