80 lines
2.9 KiB
Plaintext
80 lines
2.9 KiB
Plaintext
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SAMSUNG Exynos SoCs SROM Controller driver.
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Required properties:
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- compatible : Should contain "samsung,exynos4210-srom".
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- reg: offset and length of the register set
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Optional properties:
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The SROM controller can be used to attach external peripherals. In this case
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extra properties, describing the bus behind it, should be specified as below:
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- #address-cells: Must be set to 2 to allow device address translation.
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Address is specified as (bank#, offset).
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- #size-cells: Must be set to 1 to allow device size passing
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- ranges: Must be set up to reflect the memory layout with four integer values
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per bank:
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<bank-number> 0 <parent address of bank> <size>
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Sub-nodes:
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The actual device nodes should be added as subnodes to the SROMc node. These
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subnodes, in addition to regular device specification, should contain the following
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properties, describing configuration of the relevant SROM bank:
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Required properties:
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- reg: bank number, base address (relative to start of the bank) and size of
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the memory mapped for the device. Note that base address will be
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typically 0 as this is the start of the bank.
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- samsung,srom-timing : array of 6 integers, specifying bank timings in the
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following order: Tacp, Tcah, Tcoh, Tacc, Tcos, Tacs.
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Each value is specified in cycles and has the following
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meaning and valid range:
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Tacp : Page mode access cycle at Page mode (0 - 15)
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Tcah : Address holding time after CSn (0 - 15)
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Tcoh : Chip selection hold on OEn (0 - 15)
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Tacc : Access cycle (0 - 31, the actual time is N + 1)
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Tcos : Chip selection set-up before OEn (0 - 15)
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Tacs : Address set-up before CSn (0 - 15)
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Optional properties:
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- reg-io-width : data width in bytes (1 or 2). If omitted, default of 1 is used.
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- samsung,srom-page-mode : if page mode is set, 4 data page mode will be configured,
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else normal (1 data) page mode will be set.
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Example: basic definition, no banks are configured
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memory-controller@12570000 {
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compatible = "samsung,exynos4210-srom";
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reg = <0x12570000 0x14>;
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};
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Example: SROMc with SMSC911x ethernet chip on bank 3
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memory-controller@12570000 {
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x04000000 0x20000 // Bank0
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1 0 0x05000000 0x20000 // Bank1
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2 0 0x06000000 0x20000 // Bank2
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3 0 0x07000000 0x20000>; // Bank3
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compatible = "samsung,exynos4210-srom";
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reg = <0x12570000 0x14>;
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ethernet@3,0 {
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compatible = "smsc,lan9115";
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reg = <3 0 0x10000>; // Bank 3, offset = 0
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phy-mode = "mii";
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interrupt-parent = <&gpx0>;
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interrupts = <5 8>;
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reg-io-width = <2>;
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smsc,irq-push-pull;
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smsc,force-internal-phy;
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samsung,srom-page-mode;
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samsung,srom-timing = <9 12 1 9 1 1>;
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};
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};
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