289 lines
7 KiB
C
289 lines
7 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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#include <linux/sched.h>
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#include <linux/sched/clock.h>
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#include <asm/cpufeature.h>
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#include <asm/e820/api.h>
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#include <asm/mtrr.h>
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#include <asm/msr.h>
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#include "cpu.h"
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#define ACE_PRESENT (1 << 6)
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#define ACE_ENABLED (1 << 7)
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#define ACE_FCR (1 << 28) /* MSR_VIA_FCR */
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#define RNG_PRESENT (1 << 2)
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#define RNG_ENABLED (1 << 3)
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#define RNG_ENABLE (1 << 6) /* MSR_VIA_RNG */
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#define X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW 0x00200000
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#define X86_VMX_FEATURE_PROC_CTLS_VNMI 0x00400000
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#define X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS 0x80000000
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#define X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC 0x00000001
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#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002
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#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020
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static void init_c3(struct cpuinfo_x86 *c)
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{
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u32 lo, hi;
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/* Test for Centaur Extended Feature Flags presence */
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if (cpuid_eax(0xC0000000) >= 0xC0000001) {
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u32 tmp = cpuid_edx(0xC0000001);
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/* enable ACE unit, if present and disabled */
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if ((tmp & (ACE_PRESENT | ACE_ENABLED)) == ACE_PRESENT) {
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rdmsr(MSR_VIA_FCR, lo, hi);
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lo |= ACE_FCR; /* enable ACE unit */
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wrmsr(MSR_VIA_FCR, lo, hi);
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pr_info("CPU: Enabled ACE h/w crypto\n");
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}
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/* enable RNG unit, if present and disabled */
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if ((tmp & (RNG_PRESENT | RNG_ENABLED)) == RNG_PRESENT) {
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rdmsr(MSR_VIA_RNG, lo, hi);
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lo |= RNG_ENABLE; /* enable RNG unit */
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wrmsr(MSR_VIA_RNG, lo, hi);
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pr_info("CPU: Enabled h/w RNG\n");
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}
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/* store Centaur Extended Feature Flags as
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* word 5 of the CPU capability bit array
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*/
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c->x86_capability[CPUID_C000_0001_EDX] = cpuid_edx(0xC0000001);
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}
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#ifdef CONFIG_X86_32
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/* Cyrix III family needs CX8 & PGE explicitly enabled. */
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if (c->x86_model >= 6 && c->x86_model <= 13) {
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rdmsr(MSR_VIA_FCR, lo, hi);
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lo |= (1<<1 | 1<<7);
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wrmsr(MSR_VIA_FCR, lo, hi);
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set_cpu_cap(c, X86_FEATURE_CX8);
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}
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/* Before Nehemiah, the C3's had 3dNOW! */
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if (c->x86_model >= 6 && c->x86_model < 9)
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set_cpu_cap(c, X86_FEATURE_3DNOW);
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#endif
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if (c->x86 == 0x6 && c->x86_model >= 0xf) {
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c->x86_cache_alignment = c->x86_clflush_size * 2;
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set_cpu_cap(c, X86_FEATURE_REP_GOOD);
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}
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cpu_detect_cache_sizes(c);
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}
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enum {
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ECX8 = 1<<1,
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EIERRINT = 1<<2,
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DPM = 1<<3,
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DMCE = 1<<4,
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DSTPCLK = 1<<5,
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ELINEAR = 1<<6,
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DSMC = 1<<7,
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DTLOCK = 1<<8,
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EDCTLB = 1<<8,
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EMMX = 1<<9,
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DPDC = 1<<11,
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EBRPRED = 1<<12,
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DIC = 1<<13,
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DDC = 1<<14,
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DNA = 1<<15,
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ERETSTK = 1<<16,
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E2MMX = 1<<19,
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EAMD3D = 1<<20,
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};
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static void early_init_centaur(struct cpuinfo_x86 *c)
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{
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switch (c->x86) {
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#ifdef CONFIG_X86_32
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case 5:
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/* Emulate MTRRs using Centaur's MCR. */
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set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
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break;
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#endif
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case 6:
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if (c->x86_model >= 0xf)
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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break;
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}
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_SYSENTER32);
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#endif
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if (c->x86_power & (1 << 8)) {
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set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
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set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
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}
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}
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static void centaur_detect_vmx_virtcap(struct cpuinfo_x86 *c)
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{
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u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;
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rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, vmx_msr_low, vmx_msr_high);
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msr_ctl = vmx_msr_high | vmx_msr_low;
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if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW)
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set_cpu_cap(c, X86_FEATURE_TPR_SHADOW);
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if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_VNMI)
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set_cpu_cap(c, X86_FEATURE_VNMI);
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if (msr_ctl & X86_VMX_FEATURE_PROC_CTLS_2ND_CTLS) {
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rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
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vmx_msr_low, vmx_msr_high);
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msr_ctl2 = vmx_msr_high | vmx_msr_low;
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if ((msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VIRT_APIC) &&
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(msr_ctl & X86_VMX_FEATURE_PROC_CTLS_TPR_SHADOW))
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set_cpu_cap(c, X86_FEATURE_FLEXPRIORITY);
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if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_EPT)
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set_cpu_cap(c, X86_FEATURE_EPT);
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if (msr_ctl2 & X86_VMX_FEATURE_PROC_CTLS2_VPID)
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set_cpu_cap(c, X86_FEATURE_VPID);
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}
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}
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static void init_centaur(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_32
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char *name;
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u32 fcr_set = 0;
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u32 fcr_clr = 0;
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u32 lo, hi, newlo;
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u32 aa, bb, cc, dd;
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/*
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* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
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* 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
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*/
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clear_cpu_cap(c, 0*32+31);
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#endif
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early_init_centaur(c);
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init_intel_cacheinfo(c);
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detect_num_cpu_cores(c);
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#ifdef CONFIG_X86_32
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detect_ht(c);
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#endif
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if (c->cpuid_level > 9) {
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unsigned int eax = cpuid_eax(10);
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/*
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* Check for version and the number of counters
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* Version(eax[7:0]) can't be 0;
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* Counters(eax[15:8]) should be greater than 1;
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*/
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if ((eax & 0xff) && (((eax >> 8) & 0xff) > 1))
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set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
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}
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switch (c->x86) {
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#ifdef CONFIG_X86_32
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case 5:
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switch (c->x86_model) {
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case 4:
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name = "C6";
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fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
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fcr_clr = DPDC;
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pr_notice("Disabling bugged TSC.\n");
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clear_cpu_cap(c, X86_FEATURE_TSC);
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break;
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case 8:
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switch (c->x86_stepping) {
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default:
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name = "2";
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break;
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case 7 ... 9:
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name = "2A";
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break;
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case 10 ... 15:
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name = "2B";
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break;
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}
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fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
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E2MMX|EAMD3D;
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fcr_clr = DPDC;
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break;
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case 9:
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name = "3";
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fcr_set = ECX8|DSMC|DTLOCK|EMMX|EBRPRED|ERETSTK|
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E2MMX|EAMD3D;
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fcr_clr = DPDC;
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break;
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default:
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name = "??";
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}
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rdmsr(MSR_IDT_FCR1, lo, hi);
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newlo = (lo|fcr_set) & (~fcr_clr);
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if (newlo != lo) {
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pr_info("Centaur FCR was 0x%X now 0x%X\n",
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lo, newlo);
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wrmsr(MSR_IDT_FCR1, newlo, hi);
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} else {
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pr_info("Centaur FCR is 0x%X\n", lo);
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}
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/* Emulate MTRRs using Centaur's MCR. */
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set_cpu_cap(c, X86_FEATURE_CENTAUR_MCR);
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/* Report CX8 */
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set_cpu_cap(c, X86_FEATURE_CX8);
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/* Set 3DNow! on Winchip 2 and above. */
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if (c->x86_model >= 8)
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set_cpu_cap(c, X86_FEATURE_3DNOW);
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/* See if we can find out some more. */
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if (cpuid_eax(0x80000000) >= 0x80000005) {
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/* Yes, we can. */
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cpuid(0x80000005, &aa, &bb, &cc, &dd);
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/* Add L1 data and code cache sizes. */
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c->x86_cache_size = (cc>>24)+(dd>>24);
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}
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sprintf(c->x86_model_id, "WinChip %s", name);
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break;
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#endif
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case 6:
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init_c3(c);
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break;
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}
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#ifdef CONFIG_X86_64
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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#endif
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if (cpu_has(c, X86_FEATURE_VMX))
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centaur_detect_vmx_virtcap(c);
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}
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#ifdef CONFIG_X86_32
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static unsigned int
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centaur_size_cache(struct cpuinfo_x86 *c, unsigned int size)
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{
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/* VIA C3 CPUs (670-68F) need further shifting. */
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if ((c->x86 == 6) && ((c->x86_model == 7) || (c->x86_model == 8)))
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size >>= 8;
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/*
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* There's also an erratum in Nehemiah stepping 1, which
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* returns '65KB' instead of '64KB'
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* - Note, it seems this may only be in engineering samples.
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*/
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if ((c->x86 == 6) && (c->x86_model == 9) &&
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(c->x86_stepping == 1) && (size == 65))
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size -= 1;
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return size;
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}
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#endif
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static const struct cpu_dev centaur_cpu_dev = {
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.c_vendor = "Centaur",
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.c_ident = { "CentaurHauls" },
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.c_early_init = early_init_centaur,
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.c_init = init_centaur,
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#ifdef CONFIG_X86_32
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.legacy_cache_size = centaur_size_cache,
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#endif
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.c_x86_vendor = X86_VENDOR_CENTAUR,
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};
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cpu_dev_register(centaur_cpu_dev);
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