440 lines
12 KiB
C
440 lines
12 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "amdgpu.h"
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#define MAX_KIQ_REG_WAIT 5000 /* in usecs, 5ms */
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#define MAX_KIQ_REG_BAILOUT_INTERVAL 5 /* in msecs, 5ms */
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#define MAX_KIQ_REG_TRY 20
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uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev)
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{
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uint64_t addr = adev->vm_manager.max_pfn << AMDGPU_GPU_PAGE_SHIFT;
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addr -= AMDGPU_VA_RESERVED_SIZE;
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if (addr >= AMDGPU_VA_HOLE_START)
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addr |= AMDGPU_VA_HOLE_END;
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return addr;
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}
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bool amdgpu_virt_mmio_blocked(struct amdgpu_device *adev)
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{
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/* By now all MMIO pages except mailbox are blocked */
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/* if blocking is enabled in hypervisor. Choose the */
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/* SCRATCH_REG0 to test. */
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return RREG32_NO_KIQ(0xc040) == 0xffffffff;
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}
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int amdgpu_allocate_static_csa(struct amdgpu_device *adev)
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{
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int r;
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void *ptr;
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r = amdgpu_bo_create_kernel(adev, AMDGPU_CSA_SIZE, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM, &adev->virt.csa_obj,
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&adev->virt.csa_vmid0_addr, &ptr);
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if (r)
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return r;
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memset(ptr, 0, AMDGPU_CSA_SIZE);
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return 0;
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}
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void amdgpu_free_static_csa(struct amdgpu_device *adev) {
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amdgpu_bo_free_kernel(&adev->virt.csa_obj,
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&adev->virt.csa_vmid0_addr,
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NULL);
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}
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/*
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* amdgpu_map_static_csa should be called during amdgpu_vm_init
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* it maps virtual address amdgpu_csa_vaddr() to this VM, and each command
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* submission of GFX should use this virtual address within META_DATA init
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* package to support SRIOV gfx preemption.
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*/
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int amdgpu_map_static_csa(struct amdgpu_device *adev, struct amdgpu_vm *vm,
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struct amdgpu_bo_va **bo_va)
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{
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uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_VA_HOLE_MASK;
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struct ww_acquire_ctx ticket;
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struct list_head list;
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struct amdgpu_bo_list_entry pd;
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struct ttm_validate_buffer csa_tv;
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int r;
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INIT_LIST_HEAD(&list);
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INIT_LIST_HEAD(&csa_tv.head);
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csa_tv.bo = &adev->virt.csa_obj->tbo;
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csa_tv.shared = true;
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list_add(&csa_tv.head, &list);
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amdgpu_vm_get_pd_bo(vm, &list, &pd);
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r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL);
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if (r) {
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DRM_ERROR("failed to reserve CSA,PD BOs: err=%d\n", r);
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return r;
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}
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*bo_va = amdgpu_vm_bo_add(adev, vm, adev->virt.csa_obj);
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if (!*bo_va) {
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ttm_eu_backoff_reservation(&ticket, &list);
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DRM_ERROR("failed to create bo_va for static CSA\n");
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return -ENOMEM;
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}
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r = amdgpu_vm_alloc_pts(adev, (*bo_va)->base.vm, csa_addr,
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AMDGPU_CSA_SIZE);
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if (r) {
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DRM_ERROR("failed to allocate pts for static CSA, err=%d\n", r);
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amdgpu_vm_bo_rmv(adev, *bo_va);
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ttm_eu_backoff_reservation(&ticket, &list);
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return r;
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}
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r = amdgpu_vm_bo_map(adev, *bo_va, csa_addr, 0, AMDGPU_CSA_SIZE,
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AMDGPU_PTE_READABLE | AMDGPU_PTE_WRITEABLE |
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AMDGPU_PTE_EXECUTABLE);
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if (r) {
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DRM_ERROR("failed to do bo_map on static CSA, err=%d\n", r);
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amdgpu_vm_bo_rmv(adev, *bo_va);
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ttm_eu_backoff_reservation(&ticket, &list);
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return r;
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}
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ttm_eu_backoff_reservation(&ticket, &list);
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return 0;
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}
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void amdgpu_virt_init_setting(struct amdgpu_device *adev)
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{
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/* enable virtual display */
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adev->mode_info.num_crtc = 1;
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adev->enable_virtual_display = true;
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adev->cg_flags = 0;
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adev->pg_flags = 0;
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}
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uint32_t amdgpu_virt_kiq_rreg(struct amdgpu_device *adev, uint32_t reg)
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{
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signed long r, cnt = 0;
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unsigned long flags;
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uint32_t seq;
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struct amdgpu_kiq *kiq = &adev->gfx.kiq;
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struct amdgpu_ring *ring = &kiq->ring;
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BUG_ON(!ring->funcs->emit_rreg);
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spin_lock_irqsave(&kiq->ring_lock, flags);
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amdgpu_ring_alloc(ring, 32);
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amdgpu_ring_emit_rreg(ring, reg);
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amdgpu_fence_emit_polling(ring, &seq);
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amdgpu_ring_commit(ring);
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spin_unlock_irqrestore(&kiq->ring_lock, flags);
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r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
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/* don't wait anymore for gpu reset case because this way may
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* block gpu_recover() routine forever, e.g. this virt_kiq_rreg
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* is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
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* never return if we keep waiting in virt_kiq_rreg, which cause
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* gpu_recover() hang there.
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*
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* also don't wait anymore for IRQ context
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* */
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if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
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goto failed_kiq_read;
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if (in_interrupt())
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might_sleep();
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while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
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msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
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r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
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}
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if (cnt > MAX_KIQ_REG_TRY)
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goto failed_kiq_read;
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return adev->wb.wb[adev->virt.reg_val_offs];
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failed_kiq_read:
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pr_err("failed to read reg:%x\n", reg);
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return ~0;
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}
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void amdgpu_virt_kiq_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v)
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{
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signed long r, cnt = 0;
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unsigned long flags;
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uint32_t seq;
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struct amdgpu_kiq *kiq = &adev->gfx.kiq;
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struct amdgpu_ring *ring = &kiq->ring;
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BUG_ON(!ring->funcs->emit_wreg);
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spin_lock_irqsave(&kiq->ring_lock, flags);
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amdgpu_ring_alloc(ring, 32);
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amdgpu_ring_emit_wreg(ring, reg, v);
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amdgpu_fence_emit_polling(ring, &seq);
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amdgpu_ring_commit(ring);
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spin_unlock_irqrestore(&kiq->ring_lock, flags);
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r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
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/* don't wait anymore for gpu reset case because this way may
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* block gpu_recover() routine forever, e.g. this virt_kiq_rreg
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* is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
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* never return if we keep waiting in virt_kiq_rreg, which cause
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* gpu_recover() hang there.
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*
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* also don't wait anymore for IRQ context
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* */
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if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
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goto failed_kiq_write;
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if (in_interrupt())
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might_sleep();
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while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
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msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
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r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
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}
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if (cnt > MAX_KIQ_REG_TRY)
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goto failed_kiq_write;
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return;
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failed_kiq_write:
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pr_err("failed to write reg:%x\n", reg);
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}
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/**
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* amdgpu_virt_request_full_gpu() - request full gpu access
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* @amdgpu: amdgpu device.
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* @init: is driver init time.
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* When start to init/fini driver, first need to request full gpu access.
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* Return: Zero if request success, otherwise will return error.
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*/
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int amdgpu_virt_request_full_gpu(struct amdgpu_device *adev, bool init)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->req_full_gpu) {
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r = virt->ops->req_full_gpu(adev, init);
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if (r)
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return r;
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adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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/**
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* amdgpu_virt_release_full_gpu() - release full gpu access
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* @amdgpu: amdgpu device.
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* @init: is driver init time.
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* When finishing driver init/fini, need to release full gpu access.
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* Return: Zero if release success, otherwise will returen error.
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*/
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int amdgpu_virt_release_full_gpu(struct amdgpu_device *adev, bool init)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->rel_full_gpu) {
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r = virt->ops->rel_full_gpu(adev, init);
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if (r)
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return r;
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adev->virt.caps |= AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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/**
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* amdgpu_virt_reset_gpu() - reset gpu
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* @amdgpu: amdgpu device.
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* Send reset command to GPU hypervisor to reset GPU that VM is using
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* Return: Zero if reset success, otherwise will return error.
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*/
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int amdgpu_virt_reset_gpu(struct amdgpu_device *adev)
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{
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struct amdgpu_virt *virt = &adev->virt;
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int r;
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if (virt->ops && virt->ops->reset_gpu) {
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r = virt->ops->reset_gpu(adev);
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if (r)
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return r;
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adev->virt.caps &= ~AMDGPU_SRIOV_CAPS_RUNTIME;
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}
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return 0;
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}
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/**
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* amdgpu_virt_wait_reset() - wait for reset gpu completed
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* @amdgpu: amdgpu device.
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* Wait for GPU reset completed.
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* Return: Zero if reset success, otherwise will return error.
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*/
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int amdgpu_virt_wait_reset(struct amdgpu_device *adev)
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{
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struct amdgpu_virt *virt = &adev->virt;
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if (!virt->ops || !virt->ops->wait_reset)
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return -EINVAL;
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return virt->ops->wait_reset(adev);
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}
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/**
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* amdgpu_virt_alloc_mm_table() - alloc memory for mm table
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* @amdgpu: amdgpu device.
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* MM table is used by UVD and VCE for its initialization
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* Return: Zero if allocate success.
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*/
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int amdgpu_virt_alloc_mm_table(struct amdgpu_device *adev)
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{
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int r;
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if (!amdgpu_sriov_vf(adev) || adev->virt.mm_table.gpu_addr)
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return 0;
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r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
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AMDGPU_GEM_DOMAIN_VRAM,
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&adev->virt.mm_table.bo,
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&adev->virt.mm_table.gpu_addr,
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(void *)&adev->virt.mm_table.cpu_addr);
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if (r) {
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DRM_ERROR("failed to alloc mm table and error = %d.\n", r);
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return r;
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}
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memset((void *)adev->virt.mm_table.cpu_addr, 0, PAGE_SIZE);
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DRM_INFO("MM table gpu addr = 0x%llx, cpu addr = %p.\n",
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adev->virt.mm_table.gpu_addr,
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adev->virt.mm_table.cpu_addr);
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return 0;
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}
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/**
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* amdgpu_virt_free_mm_table() - free mm table memory
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* @amdgpu: amdgpu device.
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* Free MM table memory
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*/
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void amdgpu_virt_free_mm_table(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
if (!amdgpu_sriov_vf(adev) || !adev->virt.mm_table.gpu_addr)
|
||
|
|
return;
|
||
|
|
|
||
|
|
amdgpu_bo_free_kernel(&adev->virt.mm_table.bo,
|
||
|
|
&adev->virt.mm_table.gpu_addr,
|
||
|
|
(void *)&adev->virt.mm_table.cpu_addr);
|
||
|
|
adev->virt.mm_table.gpu_addr = 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
int amdgpu_virt_fw_reserve_get_checksum(void *obj,
|
||
|
|
unsigned long obj_size,
|
||
|
|
unsigned int key,
|
||
|
|
unsigned int chksum)
|
||
|
|
{
|
||
|
|
unsigned int ret = key;
|
||
|
|
unsigned long i = 0;
|
||
|
|
unsigned char *pos;
|
||
|
|
|
||
|
|
pos = (char *)obj;
|
||
|
|
/* calculate checksum */
|
||
|
|
for (i = 0; i < obj_size; ++i)
|
||
|
|
ret += *(pos + i);
|
||
|
|
/* minus the chksum itself */
|
||
|
|
pos = (char *)&chksum;
|
||
|
|
for (i = 0; i < sizeof(chksum); ++i)
|
||
|
|
ret -= *(pos + i);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
uint32_t pf2vf_size = 0;
|
||
|
|
uint32_t checksum = 0;
|
||
|
|
uint32_t checkval;
|
||
|
|
char *str;
|
||
|
|
|
||
|
|
adev->virt.fw_reserve.p_pf2vf = NULL;
|
||
|
|
adev->virt.fw_reserve.p_vf2pf = NULL;
|
||
|
|
|
||
|
|
if (adev->fw_vram_usage.va != NULL) {
|
||
|
|
adev->virt.fw_reserve.p_pf2vf =
|
||
|
|
(struct amdgim_pf2vf_info_header *)(
|
||
|
|
adev->fw_vram_usage.va + AMDGIM_DATAEXCHANGE_OFFSET);
|
||
|
|
AMDGPU_FW_VRAM_PF2VF_READ(adev, header.size, &pf2vf_size);
|
||
|
|
AMDGPU_FW_VRAM_PF2VF_READ(adev, checksum, &checksum);
|
||
|
|
AMDGPU_FW_VRAM_PF2VF_READ(adev, feature_flags, &adev->virt.gim_feature);
|
||
|
|
|
||
|
|
/* pf2vf message must be in 4K */
|
||
|
|
if (pf2vf_size > 0 && pf2vf_size < 4096) {
|
||
|
|
checkval = amdgpu_virt_fw_reserve_get_checksum(
|
||
|
|
adev->virt.fw_reserve.p_pf2vf, pf2vf_size,
|
||
|
|
adev->virt.fw_reserve.checksum_key, checksum);
|
||
|
|
if (checkval == checksum) {
|
||
|
|
adev->virt.fw_reserve.p_vf2pf =
|
||
|
|
((void *)adev->virt.fw_reserve.p_pf2vf +
|
||
|
|
pf2vf_size);
|
||
|
|
memset((void *)adev->virt.fw_reserve.p_vf2pf, 0,
|
||
|
|
sizeof(amdgim_vf2pf_info));
|
||
|
|
AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.version,
|
||
|
|
AMDGPU_FW_VRAM_VF2PF_VER);
|
||
|
|
AMDGPU_FW_VRAM_VF2PF_WRITE(adev, header.size,
|
||
|
|
sizeof(amdgim_vf2pf_info));
|
||
|
|
AMDGPU_FW_VRAM_VF2PF_READ(adev, driver_version,
|
||
|
|
&str);
|
||
|
|
#ifdef MODULE
|
||
|
|
if (THIS_MODULE->version != NULL)
|
||
|
|
strcpy(str, THIS_MODULE->version);
|
||
|
|
else
|
||
|
|
#endif
|
||
|
|
strcpy(str, "N/A");
|
||
|
|
AMDGPU_FW_VRAM_VF2PF_WRITE(adev, driver_cert,
|
||
|
|
0);
|
||
|
|
AMDGPU_FW_VRAM_VF2PF_WRITE(adev, checksum,
|
||
|
|
amdgpu_virt_fw_reserve_get_checksum(
|
||
|
|
adev->virt.fw_reserve.p_vf2pf,
|
||
|
|
pf2vf_size,
|
||
|
|
adev->virt.fw_reserve.checksum_key, 0));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|