464 lines
12 KiB
C
464 lines
12 KiB
C
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_ih.h"
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#include "vid.h"
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#include "oss/oss_3_0_1_d.h"
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#include "oss/oss_3_0_1_sh_mask.h"
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#include "bif/bif_5_1_d.h"
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#include "bif/bif_5_1_sh_mask.h"
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/*
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* Interrupts
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* Starting with r6xx, interrupts are handled via a ring buffer.
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* Ring buffers are areas of GPU accessible memory that the GPU
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* writes interrupt vectors into and the host reads vectors out of.
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* There is a rptr (read pointer) that determines where the
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* host is currently reading, and a wptr (write pointer)
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* which determines where the GPU has written. When the
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* pointers are equal, the ring is idle. When the GPU
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* writes vectors to the ring buffer, it increments the
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* wptr. When there is an interrupt, the host then starts
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* fetching commands and processing them until the pointers are
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* equal again at which point it updates the rptr.
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*/
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static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev);
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/**
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* cz_ih_enable_interrupts - Enable the interrupt ring buffer
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*
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* @adev: amdgpu_device pointer
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*
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* Enable the interrupt ring buffer (VI).
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*/
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static void cz_ih_enable_interrupts(struct amdgpu_device *adev)
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{
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u32 ih_cntl = RREG32(mmIH_CNTL);
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u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
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ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 1);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 1);
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WREG32(mmIH_CNTL, ih_cntl);
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WREG32(mmIH_RB_CNTL, ih_rb_cntl);
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adev->irq.ih.enabled = true;
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}
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/**
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* cz_ih_disable_interrupts - Disable the interrupt ring buffer
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*
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* @adev: amdgpu_device pointer
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*
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* Disable the interrupt ring buffer (VI).
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*/
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static void cz_ih_disable_interrupts(struct amdgpu_device *adev)
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{
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u32 ih_rb_cntl = RREG32(mmIH_RB_CNTL);
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u32 ih_cntl = RREG32(mmIH_CNTL);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_ENABLE, 0);
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ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, ENABLE_INTR, 0);
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WREG32(mmIH_RB_CNTL, ih_rb_cntl);
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WREG32(mmIH_CNTL, ih_cntl);
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/* set rptr, wptr to 0 */
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WREG32(mmIH_RB_RPTR, 0);
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WREG32(mmIH_RB_WPTR, 0);
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adev->irq.ih.enabled = false;
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adev->irq.ih.rptr = 0;
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}
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/**
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* cz_ih_irq_init - init and enable the interrupt ring
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*
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* @adev: amdgpu_device pointer
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*
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* Allocate a ring buffer for the interrupt controller,
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* enable the RLC, disable interrupts, enable the IH
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* ring buffer and enable it (VI).
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* Called at device load and reume.
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* Returns 0 for success, errors for failure.
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*/
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static int cz_ih_irq_init(struct amdgpu_device *adev)
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{
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int rb_bufsz;
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u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
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u64 wptr_off;
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/* disable irqs */
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cz_ih_disable_interrupts(adev);
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/* setup interrupt control */
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WREG32(mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
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interrupt_cntl = RREG32(mmINTERRUPT_CNTL);
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/* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
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* INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
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*/
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interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
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/* INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
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interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
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WREG32(mmINTERRUPT_CNTL, interrupt_cntl);
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/* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
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WREG32(mmIH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
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rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
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ih_rb_cntl = REG_SET_FIELD(0, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 1);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
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/* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register value is written to memory */
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ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, WPTR_WRITEBACK_ENABLE, 1);
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/* set the writeback address whether it's enabled or not */
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wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
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WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
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WREG32(mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
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WREG32(mmIH_RB_CNTL, ih_rb_cntl);
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/* set rptr, wptr to 0 */
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WREG32(mmIH_RB_RPTR, 0);
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WREG32(mmIH_RB_WPTR, 0);
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/* Default settings for IH_CNTL (disabled at first) */
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ih_cntl = RREG32(mmIH_CNTL);
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ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, MC_VMID, 0);
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if (adev->irq.msi_enabled)
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ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL, RPTR_REARM, 1);
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WREG32(mmIH_CNTL, ih_cntl);
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pci_set_master(adev->pdev);
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/* enable interrupts */
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cz_ih_enable_interrupts(adev);
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return 0;
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}
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/**
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* cz_ih_irq_disable - disable interrupts
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*
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* @adev: amdgpu_device pointer
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*
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* Disable interrupts on the hw (VI).
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*/
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static void cz_ih_irq_disable(struct amdgpu_device *adev)
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{
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cz_ih_disable_interrupts(adev);
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/* Wait and acknowledge irq */
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mdelay(1);
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}
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/**
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* cz_ih_get_wptr - get the IH ring buffer wptr
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*
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* @adev: amdgpu_device pointer
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*
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* Get the IH ring buffer wptr from either the register
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* or the writeback memory buffer (VI). Also check for
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* ring buffer overflow and deal with it.
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* Used by cz_irq_process(VI).
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* Returns the value of the wptr.
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*/
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static u32 cz_ih_get_wptr(struct amdgpu_device *adev)
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{
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u32 wptr, tmp;
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wptr = le32_to_cpu(adev->wb.wb[adev->irq.ih.wptr_offs]);
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if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) {
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wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
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/* When a ring buffer overflow happen start parsing interrupt
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* from the last not overwritten vector (wptr + 16). Hopefully
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* this should allow us to catchup.
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*/
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dev_warn(adev->dev, "IH ring buffer overflow (0x%08X, 0x%08X, 0x%08X)\n",
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wptr, adev->irq.ih.rptr, (wptr + 16) & adev->irq.ih.ptr_mask);
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adev->irq.ih.rptr = (wptr + 16) & adev->irq.ih.ptr_mask;
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tmp = RREG32(mmIH_RB_CNTL);
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tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
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WREG32(mmIH_RB_CNTL, tmp);
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}
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return (wptr & adev->irq.ih.ptr_mask);
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}
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/**
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* cz_ih_prescreen_iv - prescreen an interrupt vector
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*
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* @adev: amdgpu_device pointer
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*
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* Returns true if the interrupt vector should be further processed.
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*/
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static bool cz_ih_prescreen_iv(struct amdgpu_device *adev)
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{
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u32 ring_index = adev->irq.ih.rptr >> 2;
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u16 pasid;
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switch (le32_to_cpu(adev->irq.ih.ring[ring_index]) & 0xff) {
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case 146:
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case 147:
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pasid = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]) >> 16;
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if (!pasid || amdgpu_vm_pasid_fault_credit(adev, pasid))
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return true;
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break;
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default:
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/* Not a VM fault */
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return true;
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}
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adev->irq.ih.rptr += 16;
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return false;
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}
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/**
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* cz_ih_decode_iv - decode an interrupt vector
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*
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* @adev: amdgpu_device pointer
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*
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* Decodes the interrupt vector at the current rptr
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* position and also advance the position.
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*/
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static void cz_ih_decode_iv(struct amdgpu_device *adev,
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struct amdgpu_iv_entry *entry)
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{
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/* wptr/rptr are in bytes! */
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u32 ring_index = adev->irq.ih.rptr >> 2;
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uint32_t dw[4];
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dw[0] = le32_to_cpu(adev->irq.ih.ring[ring_index + 0]);
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dw[1] = le32_to_cpu(adev->irq.ih.ring[ring_index + 1]);
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dw[2] = le32_to_cpu(adev->irq.ih.ring[ring_index + 2]);
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dw[3] = le32_to_cpu(adev->irq.ih.ring[ring_index + 3]);
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entry->client_id = AMDGPU_IH_CLIENTID_LEGACY;
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entry->src_id = dw[0] & 0xff;
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entry->src_data[0] = dw[1] & 0xfffffff;
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entry->ring_id = dw[2] & 0xff;
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entry->vmid = (dw[2] >> 8) & 0xff;
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entry->pasid = (dw[2] >> 16) & 0xffff;
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/* wptr/rptr are in bytes! */
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adev->irq.ih.rptr += 16;
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}
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/**
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* cz_ih_set_rptr - set the IH ring buffer rptr
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*
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* @adev: amdgpu_device pointer
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*
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* Set the IH ring buffer rptr.
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*/
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static void cz_ih_set_rptr(struct amdgpu_device *adev)
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{
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WREG32(mmIH_RB_RPTR, adev->irq.ih.rptr);
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}
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static int cz_ih_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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int ret;
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ret = amdgpu_irq_add_domain(adev);
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if (ret)
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return ret;
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cz_ih_set_interrupt_funcs(adev);
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return 0;
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}
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static int cz_ih_sw_init(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = amdgpu_ih_ring_init(adev, 64 * 1024, false);
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if (r)
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return r;
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r = amdgpu_irq_init(adev);
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return r;
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}
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static int cz_ih_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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amdgpu_irq_fini(adev);
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amdgpu_ih_ring_fini(adev);
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amdgpu_irq_remove_domain(adev);
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return 0;
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}
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static int cz_ih_hw_init(void *handle)
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{
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int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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r = cz_ih_irq_init(adev);
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if (r)
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return r;
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return 0;
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}
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static int cz_ih_hw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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cz_ih_irq_disable(adev);
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return 0;
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}
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static int cz_ih_suspend(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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return cz_ih_hw_fini(adev);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int cz_ih_resume(void *handle)
|
||
|
|
{
|
||
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||
|
|
|
||
|
|
return cz_ih_hw_init(adev);
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool cz_ih_is_idle(void *handle)
|
||
|
|
{
|
||
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||
|
|
u32 tmp = RREG32(mmSRBM_STATUS);
|
||
|
|
|
||
|
|
if (REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
|
||
|
|
return false;
|
||
|
|
|
||
|
|
return true;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int cz_ih_wait_for_idle(void *handle)
|
||
|
|
{
|
||
|
|
unsigned i;
|
||
|
|
u32 tmp;
|
||
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||
|
|
|
||
|
|
for (i = 0; i < adev->usec_timeout; i++) {
|
||
|
|
/* read MC_STATUS */
|
||
|
|
tmp = RREG32(mmSRBM_STATUS);
|
||
|
|
if (!REG_GET_FIELD(tmp, SRBM_STATUS, IH_BUSY))
|
||
|
|
return 0;
|
||
|
|
udelay(1);
|
||
|
|
}
|
||
|
|
return -ETIMEDOUT;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int cz_ih_soft_reset(void *handle)
|
||
|
|
{
|
||
|
|
u32 srbm_soft_reset = 0;
|
||
|
|
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||
|
|
u32 tmp = RREG32(mmSRBM_STATUS);
|
||
|
|
|
||
|
|
if (tmp & SRBM_STATUS__IH_BUSY_MASK)
|
||
|
|
srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET,
|
||
|
|
SOFT_RESET_IH, 1);
|
||
|
|
|
||
|
|
if (srbm_soft_reset) {
|
||
|
|
tmp = RREG32(mmSRBM_SOFT_RESET);
|
||
|
|
tmp |= srbm_soft_reset;
|
||
|
|
dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
|
||
|
|
WREG32(mmSRBM_SOFT_RESET, tmp);
|
||
|
|
tmp = RREG32(mmSRBM_SOFT_RESET);
|
||
|
|
|
||
|
|
udelay(50);
|
||
|
|
|
||
|
|
tmp &= ~srbm_soft_reset;
|
||
|
|
WREG32(mmSRBM_SOFT_RESET, tmp);
|
||
|
|
tmp = RREG32(mmSRBM_SOFT_RESET);
|
||
|
|
|
||
|
|
/* Wait a little for things to settle down */
|
||
|
|
udelay(50);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int cz_ih_set_clockgating_state(void *handle,
|
||
|
|
enum amd_clockgating_state state)
|
||
|
|
{
|
||
|
|
// TODO
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int cz_ih_set_powergating_state(void *handle,
|
||
|
|
enum amd_powergating_state state)
|
||
|
|
{
|
||
|
|
// TODO
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct amd_ip_funcs cz_ih_ip_funcs = {
|
||
|
|
.name = "cz_ih",
|
||
|
|
.early_init = cz_ih_early_init,
|
||
|
|
.late_init = NULL,
|
||
|
|
.sw_init = cz_ih_sw_init,
|
||
|
|
.sw_fini = cz_ih_sw_fini,
|
||
|
|
.hw_init = cz_ih_hw_init,
|
||
|
|
.hw_fini = cz_ih_hw_fini,
|
||
|
|
.suspend = cz_ih_suspend,
|
||
|
|
.resume = cz_ih_resume,
|
||
|
|
.is_idle = cz_ih_is_idle,
|
||
|
|
.wait_for_idle = cz_ih_wait_for_idle,
|
||
|
|
.soft_reset = cz_ih_soft_reset,
|
||
|
|
.set_clockgating_state = cz_ih_set_clockgating_state,
|
||
|
|
.set_powergating_state = cz_ih_set_powergating_state,
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct amdgpu_ih_funcs cz_ih_funcs = {
|
||
|
|
.get_wptr = cz_ih_get_wptr,
|
||
|
|
.prescreen_iv = cz_ih_prescreen_iv,
|
||
|
|
.decode_iv = cz_ih_decode_iv,
|
||
|
|
.set_rptr = cz_ih_set_rptr
|
||
|
|
};
|
||
|
|
|
||
|
|
static void cz_ih_set_interrupt_funcs(struct amdgpu_device *adev)
|
||
|
|
{
|
||
|
|
if (adev->irq.ih_funcs == NULL)
|
||
|
|
adev->irq.ih_funcs = &cz_ih_funcs;
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct amdgpu_ip_block_version cz_ih_ip_block =
|
||
|
|
{
|
||
|
|
.type = AMD_IP_BLOCK_TYPE_IH,
|
||
|
|
.major = 3,
|
||
|
|
.minor = 0,
|
||
|
|
.rev = 0,
|
||
|
|
.funcs = &cz_ih_ip_funcs,
|
||
|
|
};
|