302 lines
7.9 KiB
C
302 lines
7.9 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (C) 2015-2018 Broadcom */
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#include <linux/reservation.h>
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#include <linux/mm_types.h>
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#include <drm/drmP.h>
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#include <drm/drm_encoder.h>
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#include <drm/drm_gem.h>
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#include <drm/gpu_scheduler.h>
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#define GMP_GRANULARITY (128 * 1024)
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/* Enum for each of the V3D queues. We maintain various queue
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* tracking as an array because at some point we'll want to support
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* the TFU (texture formatting unit) as another queue.
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*/
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enum v3d_queue {
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V3D_BIN,
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V3D_RENDER,
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};
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#define V3D_MAX_QUEUES (V3D_RENDER + 1)
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struct v3d_queue_state {
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struct drm_gpu_scheduler sched;
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u64 fence_context;
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u64 emit_seqno;
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};
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struct v3d_dev {
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struct drm_device drm;
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/* Short representation (e.g. 33, 41) of the V3D tech version
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* and revision.
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*/
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int ver;
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struct device *dev;
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struct platform_device *pdev;
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void __iomem *hub_regs;
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void __iomem *core_regs[3];
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void __iomem *bridge_regs;
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void __iomem *gca_regs;
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struct clk *clk;
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/* Virtual and DMA addresses of the single shared page table. */
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volatile u32 *pt;
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dma_addr_t pt_paddr;
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/* Virtual and DMA addresses of the MMU's scratch page. When
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* a read or write is invalid in the MMU, it will be
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* redirected here.
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*/
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void *mmu_scratch;
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dma_addr_t mmu_scratch_paddr;
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/* Number of V3D cores. */
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u32 cores;
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/* Allocator managing the address space. All units are in
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* number of pages.
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*/
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struct drm_mm mm;
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spinlock_t mm_lock;
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struct work_struct overflow_mem_work;
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struct v3d_exec_info *bin_job;
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struct v3d_exec_info *render_job;
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struct v3d_queue_state queue[V3D_MAX_QUEUES];
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/* Spinlock used to synchronize the overflow memory
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* management against bin job submission.
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*/
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spinlock_t job_lock;
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/* Protects bo_stats */
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struct mutex bo_lock;
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/* Lock taken when resetting the GPU, to keep multiple
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* processes from trying to park the scheduler threads and
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* reset at once.
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*/
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struct mutex reset_lock;
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/* Lock taken when creating and pushing the GPU scheduler
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* jobs, to keep the sched-fence seqnos in order.
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*/
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struct mutex sched_lock;
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struct {
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u32 num_allocated;
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u32 pages_allocated;
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} bo_stats;
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};
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static inline struct v3d_dev *
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to_v3d_dev(struct drm_device *dev)
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{
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return (struct v3d_dev *)dev->dev_private;
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}
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/* The per-fd struct, which tracks the MMU mappings. */
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struct v3d_file_priv {
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struct v3d_dev *v3d;
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struct drm_sched_entity sched_entity[V3D_MAX_QUEUES];
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};
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/* Tracks a mapping of a BO into a per-fd address space */
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struct v3d_vma {
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struct v3d_page_table *pt;
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struct list_head list; /* entry in v3d_bo.vmas */
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};
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struct v3d_bo {
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struct drm_gem_object base;
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struct mutex lock;
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struct drm_mm_node node;
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u32 pages_refcount;
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struct page **pages;
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struct sg_table *sgt;
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void *vaddr;
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struct list_head vmas; /* list of v3d_vma */
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/* List entry for the BO's position in
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* v3d_exec_info->unref_list
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*/
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struct list_head unref_head;
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/* normally (resv == &_resv) except for imported bo's */
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struct reservation_object *resv;
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struct reservation_object _resv;
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};
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static inline struct v3d_bo *
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to_v3d_bo(struct drm_gem_object *bo)
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{
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return (struct v3d_bo *)bo;
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}
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struct v3d_fence {
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struct dma_fence base;
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struct drm_device *dev;
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/* v3d seqno for signaled() test */
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u64 seqno;
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enum v3d_queue queue;
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};
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static inline struct v3d_fence *
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to_v3d_fence(struct dma_fence *fence)
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{
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return (struct v3d_fence *)fence;
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}
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#define V3D_READ(offset) readl(v3d->hub_regs + offset)
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#define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
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#define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
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#define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
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#define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
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#define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
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#define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
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#define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
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struct v3d_job {
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struct drm_sched_job base;
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struct v3d_exec_info *exec;
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/* An optional fence userspace can pass in for the job to depend on. */
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struct dma_fence *in_fence;
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/* v3d fence to be signaled by IRQ handler when the job is complete. */
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struct dma_fence *done_fence;
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/* GPU virtual addresses of the start/end of the CL job. */
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u32 start, end;
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u32 timedout_ctca, timedout_ctra;
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};
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struct v3d_exec_info {
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struct v3d_dev *v3d;
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struct v3d_job bin, render;
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/* Fence for when the scheduler considers the binner to be
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* done, for render to depend on.
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*/
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struct dma_fence *bin_done_fence;
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struct kref refcount;
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/* This is the array of BOs that were looked up at the start of exec. */
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struct v3d_bo **bo;
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u32 bo_count;
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/* List of overflow BOs used in the job that need to be
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* released once the job is complete.
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*/
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struct list_head unref_list;
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/* Submitted tile memory allocation start/size, tile state. */
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u32 qma, qms, qts;
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};
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/**
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* _wait_for - magic (register) wait macro
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*
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* Does the right thing for modeset paths when run under kdgb or similar atomic
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* contexts. Note that it's important that we check the condition again after
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* having timed out, since the timeout could be due to preemption or similar and
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* we've never had a chance to check the condition before the timeout.
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*/
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#define wait_for(COND, MS) ({ \
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unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \
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int ret__ = 0; \
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while (!(COND)) { \
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if (time_after(jiffies, timeout__)) { \
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if (!(COND)) \
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ret__ = -ETIMEDOUT; \
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break; \
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} \
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msleep(1); \
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} \
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ret__; \
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})
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static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
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{
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/* nsecs_to_jiffies64() does not guard against overflow */
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if (NSEC_PER_SEC % HZ &&
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div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
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return MAX_JIFFY_OFFSET;
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return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
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}
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/* v3d_bo.c */
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void v3d_free_object(struct drm_gem_object *gem_obj);
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struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv,
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size_t size);
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int v3d_create_bo_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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vm_fault_t v3d_gem_fault(struct vm_fault *vmf);
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int v3d_mmap(struct file *filp, struct vm_area_struct *vma);
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struct reservation_object *v3d_prime_res_obj(struct drm_gem_object *obj);
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int v3d_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma);
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struct sg_table *v3d_prime_get_sg_table(struct drm_gem_object *obj);
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struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev,
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struct dma_buf_attachment *attach,
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struct sg_table *sgt);
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/* v3d_debugfs.c */
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int v3d_debugfs_init(struct drm_minor *minor);
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/* v3d_fence.c */
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extern const struct dma_fence_ops v3d_fence_ops;
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struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
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/* v3d_gem.c */
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int v3d_gem_init(struct drm_device *dev);
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void v3d_gem_destroy(struct drm_device *dev);
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int v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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int v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv);
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void v3d_exec_put(struct v3d_exec_info *exec);
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void v3d_reset(struct v3d_dev *v3d);
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void v3d_invalidate_caches(struct v3d_dev *v3d);
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void v3d_flush_caches(struct v3d_dev *v3d);
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/* v3d_irq.c */
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int v3d_irq_init(struct v3d_dev *v3d);
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void v3d_irq_enable(struct v3d_dev *v3d);
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void v3d_irq_disable(struct v3d_dev *v3d);
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void v3d_irq_reset(struct v3d_dev *v3d);
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/* v3d_mmu.c */
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int v3d_mmu_get_offset(struct drm_file *file_priv, struct v3d_bo *bo,
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u32 *offset);
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int v3d_mmu_set_page_table(struct v3d_dev *v3d);
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void v3d_mmu_insert_ptes(struct v3d_bo *bo);
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void v3d_mmu_remove_ptes(struct v3d_bo *bo);
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/* v3d_sched.c */
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int v3d_sched_init(struct v3d_dev *v3d);
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void v3d_sched_fini(struct v3d_dev *v3d);
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