100 lines
3.3 KiB
Plaintext
100 lines
3.3 KiB
Plaintext
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General Purpose I2C Bus Mux
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This binding describes an I2C bus multiplexer that uses a mux controller
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from the mux subsystem to route the I2C signals.
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.-----. .-----.
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| dev | | dev |
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.------------. '-----' '-----'
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| SoC | | |
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| | .--------+--------'
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| .------. | .------+ child bus A, on MUX value set to 0
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| | I2C |-|--| Mux |
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| '------' | '--+---+ child bus B, on MUX value set to 1
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| .------. | | '----------+--------+--------.
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| | MUX- | | | | | |
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| | Ctrl |-|-----+ .-----. .-----. .-----.
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| '------' | | dev | | dev | | dev |
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'------------' '-----' '-----' '-----'
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Required properties:
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- compatible: i2c-mux
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- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
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port is connected to.
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- mux-controls: The phandle of the mux controller to use for operating the
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mux.
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* Standard I2C mux properties. See i2c-mux.txt in this directory.
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* I2C child bus nodes. See i2c-mux.txt in this directory. The sub-bus number
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is also the mux-controller state described in ../mux/mux-controller.txt
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Optional properties:
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- mux-locked: If present, explicitly allow unrelated I2C transactions on the
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parent I2C adapter at these times:
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+ during setup of the multiplexer
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+ between setup of the multiplexer and the child bus I2C transaction
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+ between the child bus I2C transaction and releasing of the multiplexer
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+ during releasing of the multiplexer
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However, I2C transactions to devices behind all I2C multiplexers connected
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to the same parent adapter that this multiplexer is connected to are blocked
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for the full duration of the complete multiplexed I2C transaction (i.e.
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including the times covered by the above list).
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If mux-locked is not present, the multiplexer is assumed to be parent-locked.
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This means that no unrelated I2C transactions are allowed on the parent I2C
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adapter for the complete multiplexed I2C transaction.
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The properties of mux-locked and parent-locked multiplexers are discussed
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in more detail in Documentation/i2c/i2c-topology.
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For each i2c child node, an I2C child bus will be created. They will
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be numbered based on their order in the device tree.
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Whenever an access is made to a device on a child bus, the value set
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in the relevant node's reg property will be set as the state in the
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mux controller.
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Example:
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mux: mux-controller {
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compatible = "gpio-mux";
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#mux-control-cells = <0>;
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mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
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<&pioA 1 GPIO_ACTIVE_HIGH>;
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};
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i2c-mux {
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compatible = "i2c-mux";
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mux-locked;
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i2c-parent = <&i2c1>;
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mux-controls = <&mux>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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ssd1307: oled@3c {
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compatible = "solomon,ssd1307fb-i2c";
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reg = <0x3c>;
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pwms = <&pwm 4 3000>;
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reset-gpios = <&gpio2 7 1>;
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reset-active-low;
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};
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};
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i2c@3 {
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reg = <3>;
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#address-cells = <1>;
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#size-cells = <0>;
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pca9555: pca9555@20 {
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compatible = "nxp,pca9555";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x20>;
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};
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};
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};
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