105 lines
4.3 KiB
Plaintext
105 lines
4.3 KiB
Plaintext
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Mediatek Video Codec
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Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
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supports high resolution encoding and decoding functionalities.
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Required properties:
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- compatible : "mediatek,mt8173-vcodec-enc" for encoder
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"mediatek,mt8173-vcodec-dec" for decoder.
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- reg : Physical base address of the video codec registers and length of
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memory mapped region.
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- interrupts : interrupt number to the cpu.
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- clocks : list of clock specifiers, corresponding to entries in
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the clock-names property.
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- clock-names: encoder must contain "venc_sel_src", "venc_sel",,
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"venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll",
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"univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll",
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"venc_lt_sel", "vdec_bus_clk_src".
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- iommus : should point to the respective IOMMU block with master port as
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argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt
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for details.
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- mediatek,vpu : the node of video processor unit
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Example:
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vcodec_dec: vcodec@16000000 {
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compatible = "mediatek,mt8173-vcodec-dec";
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reg = <0 0x16000000 0 0x100>, /*VDEC_SYS*/
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<0 0x16020000 0 0x1000>, /*VDEC_MISC*/
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<0 0x16021000 0 0x800>, /*VDEC_LD*/
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<0 0x16021800 0 0x800>, /*VDEC_TOP*/
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<0 0x16022000 0 0x1000>, /*VDEC_CM*/
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<0 0x16023000 0 0x1000>, /*VDEC_AD*/
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<0 0x16024000 0 0x1000>, /*VDEC_AV*/
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<0 0x16025000 0 0x1000>, /*VDEC_PP*/
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<0 0x16026800 0 0x800>, /*VP8_VD*/
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<0 0x16027000 0 0x800>, /*VP6_VD*/
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<0 0x16027800 0 0x800>, /*VP8_VL*/
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<0 0x16028400 0 0x400>; /*VP9_VD*/
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interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
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iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
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<&iommu M4U_PORT_HW_VDEC_PP_EXT>,
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<&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
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<&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
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<&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
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<&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
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<&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
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<&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
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mediatek,vpu = <&vpu>;
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power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
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clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
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<&topckgen CLK_TOP_UNIVPLL_D2>,
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<&topckgen CLK_TOP_CCI400_SEL>,
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<&topckgen CLK_TOP_VDEC_SEL>,
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<&topckgen CLK_TOP_VCODECPLL>,
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<&apmixedsys CLK_APMIXED_VENCPLL>,
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<&topckgen CLK_TOP_VENC_LT_SEL>,
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<&topckgen CLK_TOP_VCODECPLL_370P5>;
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clock-names = "vcodecpll",
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"univpll_d2",
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"clk_cci400_sel",
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"vdec_sel",
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"vdecpll",
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"vencpll",
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"venc_lt_sel",
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"vdec_bus_clk_src";
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};
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vcodec_enc: vcodec@18002000 {
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compatible = "mediatek,mt8173-vcodec-enc";
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reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/
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<0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
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iommus = <&iommu M4U_PORT_VENC_RCPU>,
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<&iommu M4U_PORT_VENC_REC>,
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<&iommu M4U_PORT_VENC_BSDMA>,
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<&iommu M4U_PORT_VENC_SV_COMV>,
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<&iommu M4U_PORT_VENC_RD_COMV>,
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<&iommu M4U_PORT_VENC_CUR_LUMA>,
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<&iommu M4U_PORT_VENC_CUR_CHROMA>,
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<&iommu M4U_PORT_VENC_REF_LUMA>,
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<&iommu M4U_PORT_VENC_REF_CHROMA>,
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<&iommu M4U_PORT_VENC_NBM_RDMA>,
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<&iommu M4U_PORT_VENC_NBM_WDMA>,
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<&iommu M4U_PORT_VENC_RCPU_SET2>,
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<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
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<&iommu M4U_PORT_VENC_BSDMA_SET2>,
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<&iommu M4U_PORT_VENC_SV_COMA_SET2>,
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<&iommu M4U_PORT_VENC_RD_COMA_SET2>,
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<&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
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<&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
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<&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
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<&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
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mediatek,vpu = <&vpu>;
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clocks = <&topckgen CLK_TOP_VENCPLL_D2>,
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<&topckgen CLK_TOP_VENC_SEL>,
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<&topckgen CLK_TOP_UNIVPLL1_D2>,
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<&topckgen CLK_TOP_VENC_LT_SEL>;
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clock-names = "venc_sel_src",
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"venc_sel",
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"venc_lt_sel_src",
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"venc_lt_sel";
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};
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