178 lines
6.7 KiB
Plaintext
178 lines
6.7 KiB
Plaintext
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Renesas R-Car Gen3 Digital Radio Interface controller (DRIF)
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------------------------------------------------------------
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R-Car Gen3 DRIF is a SPI like receive only slave device. A general
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representation of DRIF interfacing with a master device is shown below.
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+---------------------+ +---------------------+
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| |-----SCK------->|CLK |
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| Master |-----SS-------->|SYNC DRIFn (slave) |
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| |-----SD0------->|D0 |
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| |-----SD1------->|D1 |
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+---------------------+ +---------------------+
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As per datasheet, each DRIF channel (drifn) is made up of two internal
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channels (drifn0 & drifn1). These two internal channels share the common
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CLK & SYNC. Each internal channel has its own dedicated resources like
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irq, dma channels, address space & clock. This internal split is not
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visible to the external master device.
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The device tree model represents each internal channel as a separate node.
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The internal channels sharing the CLK & SYNC are tied together by their
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phandles using a property called "renesas,bonding". For the rest of
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the documentation, unless explicitly stated, the word channel implies an
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internal channel.
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When both internal channels are enabled they need to be managed together
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as one (i.e.) they cannot operate alone as independent devices. Out of the
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two, one of them needs to act as a primary device that accepts common
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properties of both the internal channels. This channel is identified by a
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property called "renesas,primary-bond".
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To summarize,
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- When both the internal channels that are bonded together are enabled,
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the zeroth channel is selected as primary-bond. This channels accepts
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properties common to all the members of the bond.
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- When only one of the bonded channels need to be enabled, the property
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"renesas,bonding" or "renesas,primary-bond" will have no effect. That
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enabled channel can act alone as any other independent device.
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Required properties of an internal channel:
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-------------------------------------------
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- compatible: "renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC.
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"renesas,r8a7796-drif" if DRIF controller is a part of R8A7796 SoC.
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"renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device.
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When compatible with the generic version, nodes must list the
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SoC-specific version corresponding to the platform first
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followed by the generic version.
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- reg: offset and length of that channel.
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- interrupts: associated with that channel.
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- clocks: phandle and clock specifier of that channel.
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- clock-names: clock input name string: "fck".
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- dmas: phandles to the DMA channels.
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- dma-names: names of the DMA channel: "rx".
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- renesas,bonding: phandle to the other channel.
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Optional properties of an internal channel:
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-------------------------------------------
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- power-domains: phandle to the respective power domain.
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Required properties of an internal channel when:
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- It is the only enabled channel of the bond (or)
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- If it acts as primary among enabled bonds
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--------------------------------------------------------
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- pinctrl-0: pin control group to be used for this channel.
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- pinctrl-names: must be "default".
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- renesas,primary-bond: empty property indicating the channel acts as primary
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among the bonded channels.
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- port: child port node corresponding to the data input, in accordance with
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the video interface bindings defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The port
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node must contain at least one endpoint.
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Optional endpoint property:
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---------------------------
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- sync-active: Indicates sync signal polarity, 0/1 for low/high respectively.
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This property maps to SYNCAC bit in the hardware manual. The
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default is 1 (active high).
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Example:
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--------
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(1) Both internal channels enabled:
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-----------------------------------
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When interfacing with a third party tuner device with two data pins as shown
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below.
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+---------------------+ +---------------------+
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| |-----SCK------->|CLK |
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| Master |-----SS-------->|SYNC DRIFn (slave) |
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| |-----SD0------->|D0 |
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| |-----SD1------->|D1 |
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+---------------------+ +---------------------+
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drif00: rif@e6f40000 {
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compatible = "renesas,r8a7795-drif",
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"renesas,rcar-gen3-drif";
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reg = <0 0xe6f40000 0 0x64>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 515>;
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clock-names = "fck";
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dmas = <&dmac1 0x20>, <&dmac2 0x20>;
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dma-names = "rx", "rx";
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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renesas,bonding = <&drif01>;
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renesas,primary-bond;
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pinctrl-0 = <&drif0_pins>;
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pinctrl-names = "default";
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port {
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drif0_ep: endpoint {
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remote-endpoint = <&tuner_ep>;
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};
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};
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};
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drif01: rif@e6f50000 {
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compatible = "renesas,r8a7795-drif",
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"renesas,rcar-gen3-drif";
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reg = <0 0xe6f50000 0 0x64>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 514>;
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clock-names = "fck";
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dmas = <&dmac1 0x22>, <&dmac2 0x22>;
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dma-names = "rx", "rx";
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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renesas,bonding = <&drif00>;
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};
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(2) Internal channel 1 alone is enabled:
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----------------------------------------
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When interfacing with a third party tuner device with one data pin as shown
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below.
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+---------------------+ +---------------------+
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| |-----SCK------->|CLK |
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| Master |-----SS-------->|SYNC DRIFn (slave) |
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| | |D0 (unused) |
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| |-----SD-------->|D1 |
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+---------------------+ +---------------------+
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drif00: rif@e6f40000 {
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compatible = "renesas,r8a7795-drif",
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"renesas,rcar-gen3-drif";
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reg = <0 0xe6f40000 0 0x64>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 515>;
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clock-names = "fck";
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dmas = <&dmac1 0x20>, <&dmac2 0x20>;
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dma-names = "rx", "rx";
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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renesas,bonding = <&drif01>;
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};
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drif01: rif@e6f50000 {
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compatible = "renesas,r8a7795-drif",
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"renesas,rcar-gen3-drif";
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reg = <0 0xe6f50000 0 0x64>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 514>;
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clock-names = "fck";
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dmas = <&dmac1 0x22>, <&dmac2 0x22>;
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dma-names = "rx", "rx";
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power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
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renesas,bonding = <&drif00>;
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pinctrl-0 = <&drif0_pins>;
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pinctrl-names = "default";
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port {
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drif0_ep: endpoint {
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remote-endpoint = <&tuner_ep>;
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sync-active = <0>;
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};
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};
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};
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