26 lines
570 B
Plaintext
26 lines
570 B
Plaintext
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Timer64
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-------
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The timer64 node describes C6X event timers.
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Required properties:
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- compatible: must be "ti,c64x+timer64"
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- reg: base address and size of register region
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- interrupts: interrupt id
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Optional properties:
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- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
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- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
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Example:
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timer0: timer@25e0000 {
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compatible = "ti,c64x+timer64";
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ti,core-mask = < 0x01 >;
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reg = <0x25e0000 0x40>;
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interrupt-parent = <&megamod_pic>;
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interrupts = < 16 >;
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};
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