134 lines
3 KiB
Plaintext
134 lines
3 KiB
Plaintext
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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/**********************************************
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*MT6739 MSDC DTSI File
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********************************************/
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&msdc0 {
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index = /bits/ 8 <0>;
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clk_src = /bits/ 8 <MSDC0_CLKSRC_400MHZ>;
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bus-width = <8>;
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max-frequency = <200000000>;
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cap-mmc-highspeed;
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msdc-sys-suspend;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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non-removable;
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pinctl = <&msdc0_pins_default>;
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pinctl_hs400 = <&msdc0_pins_default>;
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pinctl_hs200 = <&msdc0_pins_default>;
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register_setting = <&msdc0_register_setting_default>;
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host_function = /bits/ 8 <MSDC_EMMC>;
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status = "okay";
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vmmc-supply = <&mt_pmic_vemc_ldo_reg>;
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clocks = <&infracfg_ao CLK_INFRA_MSDC0_SRC>, <&infracfg_ao CLK_INFRA_MSDC0>;
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clock-names = "msdc0-clock", "msdc0-hclock";
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hw_dvfs = /bits/ 8 <0>;
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};
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&msdc1 {
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index = /bits/ 8 <1>;
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clk_src = /bits/ 8 <MSDC1_CLKSRC_200MHZ>;
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bus-width = <4>;
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max-frequency = <200000000>;
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msdc-sys-suspend;
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cap-sd-highspeed;
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sd-uhs-sdr12;
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sd-uhs-sdr25;
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sd-uhs-sdr50;
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sd-uhs-sdr104;
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sd-uhs-ddr50;
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pinctl = <&msdc1_pins_default>;
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pinctl_sdr104 = <&msdc1_pins_sdr104>;
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pinctl_sdr50 = <&msdc1_pins_sdr50>;
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pinctl_ddr50 = <&msdc1_pins_ddr50>;
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register_setting = <&msdc1_register_setting_default>;
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host_function = /bits/ 8 <MSDC_SD>;
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cd_level = /bits/ 8 <MSDC_CD_LOW>;
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cd-gpios = <&pio 15 0>;
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status = "okay";
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vmmc-supply = <&mt_pmic_vmch_ldo_reg>;
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vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
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clocks = <&infracfg_ao CLK_INFRA_MSDC1_SRC>, <&infracfg_ao CLK_INFRA_MSDC1>;
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clock-names = "msdc1-clock", "msdc1-hclock";
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hw_dvfs = /bits/ 8 <0>;
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};
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&msdc0 {
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msdc0_pins_default: msdc0@default {
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pins_cmd {
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drive-strength = /bits/ 8 <4>;
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};
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pins_dat {
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drive-strength = /bits/ 8 <4>;
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};
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pins_clk {
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drive-strength = /bits/ 8 <4>;
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};
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pins_rst {
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drive-strength = /bits/ 8 <4>;
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};
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pins_ds {
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drive-strength = /bits/ 8 <4>;
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};
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};
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msdc0_register_setting_default: msdc0@register_default {
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cmd_edge = /bits/ 8 <MSDC_SMPL_RISING>;
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rdata_edge = /bits/ 8 <MSDC_SMPL_RISING>;
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wdata_edge = /bits/ 8 <MSDC_SMPL_RISING>;
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};
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};
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&msdc1 {
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msdc1_pins_default: msdc1@default {
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pins_cmd {
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drive-strength = /bits/ 8 <3>;
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};
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pins_dat {
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drive-strength = /bits/ 8 <3>;
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};
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pins_clk {
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drive-strength = /bits/ 8 <3>;
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};
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};
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msdc1_pins_sdr104: msdc1@sdr104 {
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pins_cmd {
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drive-strength = /bits/ 8 <3>;
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};
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pins_dat {
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drive-strength = /bits/ 8 <3>;
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};
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pins_clk {
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drive-strength = /bits/ 8 <3>;
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};
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};
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msdc1_pins_sdr50: msdc1@sdr50 {
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pins_cmd {
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drive-strength = /bits/ 8 <3>;
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};
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pins_dat {
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drive-strength = /bits/ 8 <3>;
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};
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pins_clk {
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drive-strength = /bits/ 8 <3>;
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};
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};
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msdc1_pins_ddr50: msdc1@ddr50 {
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pins_cmd {
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drive-strength = /bits/ 8 <3>;
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};
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pins_dat {
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drive-strength = /bits/ 8 <3>;
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};
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pins_clk {
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drive-strength = /bits/ 8 <3>;
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};
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};
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msdc1_register_setting_default: msdc1@register_default {
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cmd_edge = /bits/ 8 <MSDC_SMPL_RISING>;
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rdata_edge = /bits/ 8 <MSDC_SMPL_RISING>;
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wdata_edge = /bits/ 8 <MSDC_SMPL_RISING>;
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};
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};
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