704 lines
19 KiB
Plaintext
704 lines
19 KiB
Plaintext
|
// SPDX-License-Identifier: GPL-2.0
|
||
|
|
/*
|
||
|
|
* Copyright (c) 2019 MediaTek Inc.
|
||
|
|
*/
|
||
|
|
#include <dt-bindings/iio/mt635x-auxadc.h>
|
||
|
|
|
||
|
|
&main_pmic{
|
||
|
|
compatible = "mediatek,mt6359-pmic";
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
mediatek,num-pmic-irqs = <145>;
|
||
|
|
mediatek,pmic-irqs =
|
||
|
|
<INT_VPU_OC SP_BUCK>,
|
||
|
|
<INT_VCORE_OC SP_BUCK>,
|
||
|
|
<INT_VGPU11_OC SP_BUCK>,
|
||
|
|
<INT_VGPU12_OC SP_BUCK>,
|
||
|
|
<INT_VMODEM_OC SP_BUCK>,
|
||
|
|
<INT_VPROC1_OC SP_BUCK>,
|
||
|
|
<INT_VPROC2_OC SP_BUCK>,
|
||
|
|
<INT_VS1_OC SP_BUCK>,
|
||
|
|
<INT_VS2_OC SP_BUCK>,
|
||
|
|
<INT_VPA_OC SP_BUCK>,
|
||
|
|
<INT_VFE28_OC SP_LDO>,
|
||
|
|
<INT_VXO22_OC SP_LDO>,
|
||
|
|
<INT_VRF18_OC SP_LDO>,
|
||
|
|
<INT_VRF12_OC SP_LDO>,
|
||
|
|
<INT_VEFUSE_OC SP_LDO>,
|
||
|
|
<INT_VCN33_1_OC SP_LDO>,
|
||
|
|
<INT_VCN33_2_OC SP_LDO>,
|
||
|
|
<INT_VCN13_OC SP_LDO>,
|
||
|
|
<INT_VCN18_OC SP_LDO>,
|
||
|
|
<INT_VA09_OC SP_LDO>,
|
||
|
|
<INT_VCAMIO_OC SP_LDO>,
|
||
|
|
<INT_VA12_OC SP_LDO>,
|
||
|
|
<INT_VAUX18_OC SP_LDO>,
|
||
|
|
<INT_VAUD18_OC SP_LDO>,
|
||
|
|
<INT_VIO18_OC SP_LDO>,
|
||
|
|
<INT_VSRAM_PROC1_OC SP_LDO>,
|
||
|
|
<INT_VSRAM_PROC2_OC SP_LDO>,
|
||
|
|
<INT_VSRAM_OTHERS_OC SP_LDO>,
|
||
|
|
<INT_VSRAM_MD_OC SP_LDO>,
|
||
|
|
<INT_VEMC_OC SP_LDO>,
|
||
|
|
<INT_VSIM1_OC SP_LDO>,
|
||
|
|
<INT_VSIM2_OC SP_LDO>,
|
||
|
|
<INT_VUSB_OC SP_LDO>,
|
||
|
|
<INT_VRFCK_OC SP_LDO>,
|
||
|
|
<INT_VBBCK_OC SP_LDO>,
|
||
|
|
<INT_VBIF28_OC SP_LDO>,
|
||
|
|
<INT_VIBR_OC SP_LDO>,
|
||
|
|
<INT_VIO28_OC SP_LDO>,
|
||
|
|
<INT_VM18_OC SP_LDO>,
|
||
|
|
<INT_VUFS_OC SP_LDO>,
|
||
|
|
<INT_PWRKEY SP_PSC>,
|
||
|
|
<INT_HOMEKEY SP_PSC>,
|
||
|
|
<INT_PWRKEY_R SP_PSC>,
|
||
|
|
<INT_HOMEKEY_R SP_PSC>,
|
||
|
|
<INT_NI_LBAT_INT SP_PSC>,
|
||
|
|
<INT_CHRDET_EDGE SP_PSC>,
|
||
|
|
<INT_RTC SP_SCK>,
|
||
|
|
<INT_FG_BAT_H SP_BM>,
|
||
|
|
<INT_FG_BAT_L SP_BM>,
|
||
|
|
<INT_FG_CUR_H SP_BM>,
|
||
|
|
<INT_FG_CUR_L SP_BM>,
|
||
|
|
<INT_FG_ZCV SP_BM>,
|
||
|
|
<INT_FG_N_CHARGE_L SP_BM>,
|
||
|
|
<INT_FG_IAVG_H SP_BM>,
|
||
|
|
<INT_FG_IAVG_L SP_BM>,
|
||
|
|
<INT_FG_DISCHARGE SP_BM>,
|
||
|
|
<INT_FG_CHARGE SP_BM>,
|
||
|
|
<INT_BATON_LV SP_BM>,
|
||
|
|
<INT_BATON_BAT_IN SP_BM>,
|
||
|
|
<INT_BATON_BAT_OUT SP_BM>,
|
||
|
|
<INT_BIF SP_BM>,
|
||
|
|
<INT_BAT_H SP_HK>,
|
||
|
|
<INT_BAT_L SP_HK>,
|
||
|
|
<INT_BAT2_H SP_HK>,
|
||
|
|
<INT_BAT2_L SP_HK>,
|
||
|
|
<INT_BAT_TEMP_H SP_HK>,
|
||
|
|
<INT_BAT_TEMP_L SP_HK>,
|
||
|
|
<INT_THR_H SP_HK>,
|
||
|
|
<INT_THR_L SP_HK>,
|
||
|
|
<INT_AUXADC_IMP SP_HK>,
|
||
|
|
<INT_NAG_C_DLTV SP_HK>,
|
||
|
|
<INT_AUDIO SP_AUD>,
|
||
|
|
<INT_ACCDET SP_AUD>,
|
||
|
|
<INT_ACCDET_EINT0 SP_AUD>,
|
||
|
|
<INT_ACCDET_EINT1 SP_AUD>,
|
||
|
|
<INT_SPI_CMD_ALERT SP_MISC>;
|
||
|
|
interrupt-names =
|
||
|
|
"vpu_oc",
|
||
|
|
"vcore_oc",
|
||
|
|
"vgpu11_oc",
|
||
|
|
"vgpu12_oc",
|
||
|
|
"vmodem_oc",
|
||
|
|
"vproc1_oc",
|
||
|
|
"vproc2_oc",
|
||
|
|
"vs1_oc",
|
||
|
|
"vs2_oc",
|
||
|
|
"vpa_oc",
|
||
|
|
"vfe28_oc",
|
||
|
|
"vxo22_oc",
|
||
|
|
"vrf18_oc",
|
||
|
|
"vrf12_oc",
|
||
|
|
"vefuse_oc",
|
||
|
|
"vcn33_1_oc",
|
||
|
|
"vcn33_2_oc",
|
||
|
|
"vcn13_oc",
|
||
|
|
"vcn18_oc",
|
||
|
|
"va09_oc",
|
||
|
|
"vcamio_oc",
|
||
|
|
"va12_oc",
|
||
|
|
"vaux18_oc",
|
||
|
|
"vaud18_oc",
|
||
|
|
"vio18_oc",
|
||
|
|
"vsram_proc1_oc",
|
||
|
|
"vsram_proc2_oc",
|
||
|
|
"vsram_others_oc",
|
||
|
|
"vsram_md_oc",
|
||
|
|
"vemc_oc",
|
||
|
|
"vsim1_oc",
|
||
|
|
"vsim2_oc",
|
||
|
|
"vusb_oc",
|
||
|
|
"vrfck_oc",
|
||
|
|
"vbbck_oc",
|
||
|
|
"vbif28_oc",
|
||
|
|
"vibr_oc",
|
||
|
|
"vio28_oc",
|
||
|
|
"vm18_oc",
|
||
|
|
"vufs_oc",
|
||
|
|
"pwrkey",
|
||
|
|
"homekey",
|
||
|
|
"pwrkey_r",
|
||
|
|
"homekey_r",
|
||
|
|
"ni_lbat_int",
|
||
|
|
"chrdet_edge",
|
||
|
|
"rtc",
|
||
|
|
"fg_bat_h",
|
||
|
|
"fg_bat_l",
|
||
|
|
"fg_cur_h",
|
||
|
|
"fg_cur_l",
|
||
|
|
"fg_zcv",
|
||
|
|
"fg_n_charge_l",
|
||
|
|
"fg_iavg_h",
|
||
|
|
"fg_iavg_l",
|
||
|
|
"fg_discharge",
|
||
|
|
"fg_charge",
|
||
|
|
"baton_lv",
|
||
|
|
"baton_bat_in",
|
||
|
|
"baton_bat_out",
|
||
|
|
"bif",
|
||
|
|
"bat_h",
|
||
|
|
"bat_l",
|
||
|
|
"bat2_h",
|
||
|
|
"bat2_l",
|
||
|
|
"bat_temp_h",
|
||
|
|
"bat_temp_l",
|
||
|
|
"thr_h",
|
||
|
|
"thr_l",
|
||
|
|
"auxadc_imp",
|
||
|
|
"nag_c_dltv",
|
||
|
|
"audio",
|
||
|
|
"accdet",
|
||
|
|
"accdet_eint0",
|
||
|
|
"accdet_eint1",
|
||
|
|
"spi_cmd_alert";
|
||
|
|
|
||
|
|
pmic: mt-pmic {
|
||
|
|
compatible = "mediatek,mt-pmic";
|
||
|
|
interrupts = <INT_PWRKEY IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<INT_PWRKEY_R IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<INT_HOMEKEY IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<INT_HOMEKEY_R IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<INT_BAT_H IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<INT_BAT_L IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<INT_FG_CUR_H IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<INT_FG_CUR_L IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "pwrkey",
|
||
|
|
"pwrkey_r",
|
||
|
|
"homekey",
|
||
|
|
"homekey_r",
|
||
|
|
"bat_h",
|
||
|
|
"bat_l",
|
||
|
|
"fg_cur_h",
|
||
|
|
"fg_cur_l";
|
||
|
|
io-channels = <&pmic_auxadc AUXADC_IMP>,
|
||
|
|
<&pmic_auxadc AUXADC_IMIX_R>,
|
||
|
|
<&pmic_auxadc AUXADC_BATADC>;
|
||
|
|
io-channel-names = "pmic_ptim",
|
||
|
|
"pmic_imix_r",
|
||
|
|
"pmic_batadc";
|
||
|
|
};
|
||
|
|
|
||
|
|
/*accdet: accdet {
|
||
|
|
* compatible = "mediatek,mt6359-accdet";
|
||
|
|
* accdet-name = "mt63xx-accdet";
|
||
|
|
* accdet-mic-vol = <8>;
|
||
|
|
* accdet-plugout-debounce = <1>;
|
||
|
|
* accdet-mic-mode = <2>;
|
||
|
|
* eint_use_ext_res = <0>;
|
||
|
|
* headset-mode-setting = <0x500 0x500 1 0x1f0
|
||
|
|
* 0x800 0x800 0x20 0x44
|
||
|
|
* 0x4 0x1
|
||
|
|
* 0x5 0x3 0x3 0x5 0xe>;
|
||
|
|
* headset-use-ap-eint = <0>;
|
||
|
|
* headset-eint-num = <0>;
|
||
|
|
* headset-eint-trig-mode = <1>;
|
||
|
|
* headset-key-mode = <0>;
|
||
|
|
* headset-three-key-threshold = <0 80 220 400>;
|
||
|
|
* headset-three-key-threshold-CDD = <0 121 192 600>;
|
||
|
|
* headset-four-key-threshold = <0 58 121 192 400>;
|
||
|
|
* io-channels = <&pmic_auxadc AUXADC_ACCDET>;
|
||
|
|
* io-channel-names = "pmic_accdet";
|
||
|
|
* nvmem = <&pmic_efuse>;
|
||
|
|
* nvmem-names = "mt63xx-accdet-efuse";
|
||
|
|
* status = "okay";
|
||
|
|
* };
|
||
|
|
*/
|
||
|
|
|
||
|
|
mt6359keys: mt6359keys {
|
||
|
|
compatible = "mediatek,mt6359-keys";
|
||
|
|
mediatek,long-press-mode = <1>;
|
||
|
|
power-off-time-sec = <0>;
|
||
|
|
|
||
|
|
power {
|
||
|
|
linux,keycodes = <116>;
|
||
|
|
wakeup-source;
|
||
|
|
};
|
||
|
|
|
||
|
|
home {
|
||
|
|
linux,keycodes = <115>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
pmic_auxadc: pmic_auxadc {
|
||
|
|
compatible = "mediatek,pmic-auxadc",
|
||
|
|
"mediatek,mt6359-auxadc";
|
||
|
|
#io-channel-cells = <1>;
|
||
|
|
|
||
|
|
batadc {
|
||
|
|
channel = <AUXADC_BATADC>;
|
||
|
|
resistance-ratio = <7 2>;
|
||
|
|
avg-num = <128>;
|
||
|
|
};
|
||
|
|
bat_temp {
|
||
|
|
channel = <AUXADC_BAT_TEMP>;
|
||
|
|
resistance-ratio = <5 2>;
|
||
|
|
};
|
||
|
|
chip_temp {
|
||
|
|
channel = <AUXADC_CHIP_TEMP>;
|
||
|
|
};
|
||
|
|
vcore_temp {
|
||
|
|
channel = <AUXADC_VCORE_TEMP>;
|
||
|
|
};
|
||
|
|
vproc_temp {
|
||
|
|
channel = <AUXADC_VPROC_TEMP>;
|
||
|
|
};
|
||
|
|
vgpu_temp {
|
||
|
|
channel = <AUXADC_VGPU_TEMP>;
|
||
|
|
};
|
||
|
|
accdet {
|
||
|
|
channel = <AUXADC_ACCDET>;
|
||
|
|
};
|
||
|
|
dcxo_volt {
|
||
|
|
channel = <AUXADC_VDCXO>;
|
||
|
|
resistance-ratio = <3 2>;
|
||
|
|
};
|
||
|
|
tsx_temp {
|
||
|
|
channel = <AUXADC_TSX_TEMP>;
|
||
|
|
avg-num = <128>;
|
||
|
|
};
|
||
|
|
hpofs_cal {
|
||
|
|
channel = <AUXADC_HPOFS_CAL>;
|
||
|
|
avg-num = <256>;
|
||
|
|
};
|
||
|
|
dcxo_temp {
|
||
|
|
channel = <AUXADC_DCXO_TEMP>;
|
||
|
|
avg-num = <16>;
|
||
|
|
};
|
||
|
|
vbif {
|
||
|
|
channel = <AUXADC_VBIF>;
|
||
|
|
resistance-ratio = <5 2>;
|
||
|
|
};
|
||
|
|
imp {
|
||
|
|
channel = <AUXADC_IMP>;
|
||
|
|
resistance-ratio = <7 2>;
|
||
|
|
avg-num = <128>;
|
||
|
|
};
|
||
|
|
imix_r {
|
||
|
|
channel = <AUXADC_IMIX_R>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
mtk_gauge: mtk_gauge {
|
||
|
|
compatible = "mediatek,mt6359-gauge";
|
||
|
|
charger = <&mt6360_chg>;
|
||
|
|
bootmode = <&chosen>;
|
||
|
|
io-channels = <&pmic_auxadc AUXADC_BAT_TEMP>,
|
||
|
|
<&pmic_auxadc AUXADC_BATADC>,
|
||
|
|
<&pmic_auxadc AUXADC_VBIF>,
|
||
|
|
<&pmic_auxadc AUXADC_IMP>,
|
||
|
|
<&pmic_auxadc AUXADC_IMIX_R>;
|
||
|
|
io-channel-names = "pmic_battery_temp",
|
||
|
|
"pmic_battery_voltage",
|
||
|
|
"pmic_bif_voltage",
|
||
|
|
"pmic_ptim_voltage",
|
||
|
|
"pmic_ptim_r";
|
||
|
|
nvmem-cells = <&fg_init>, <&fg_soc>;
|
||
|
|
nvmem-cell-names = "initialization", "state-of-charge";
|
||
|
|
};
|
||
|
|
|
||
|
|
mtk_ts_pmic: mtk_ts_pmic {
|
||
|
|
compatible = "mediatek,mtk_ts_pmic";
|
||
|
|
io-channels =
|
||
|
|
<&pmic_auxadc AUXADC_CHIP_TEMP>,
|
||
|
|
<&pmic_auxadc AUXADC_VCORE_TEMP>,
|
||
|
|
<&pmic_auxadc AUXADC_VPROC_TEMP>,
|
||
|
|
<&pmic_auxadc AUXADC_VGPU_TEMP>,
|
||
|
|
<&pmic_auxadc AUXADC_TSX_TEMP>,
|
||
|
|
<&pmic_auxadc AUXADC_DCXO_TEMP>;
|
||
|
|
io-channel-names =
|
||
|
|
"pmic_chip_temp",
|
||
|
|
"pmic_buck1_temp",
|
||
|
|
"pmic_buck2_temp",
|
||
|
|
"pmic_buck3_temp",
|
||
|
|
"pmic_tsx_temp",
|
||
|
|
"pmic_dcxo_temp";
|
||
|
|
};
|
||
|
|
pmic_efuse: pmic_efuse {
|
||
|
|
compatible = "mediatek,mt6359-efuse";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
mtk_dynamic_loading_throttling {
|
||
|
|
compatible =
|
||
|
|
"mediatek,mt6359-dynamic_loading_throttling";
|
||
|
|
/*charger: mtk_charger_thread*/
|
||
|
|
mediatek,charger = <&charger>;
|
||
|
|
/*2600~2900mv ,one gear per 50mv*/
|
||
|
|
uvlo-level = <2600>;
|
||
|
|
io-channels = <&pmic_auxadc AUXADC_IMP>,
|
||
|
|
<&pmic_auxadc AUXADC_IMIX_R>,
|
||
|
|
<&pmic_auxadc AUXADC_BATADC>;
|
||
|
|
io-channel-names = "pmic_ptim",
|
||
|
|
"pmic_imix_r",
|
||
|
|
"pmic_batadc";
|
||
|
|
};
|
||
|
|
|
||
|
|
pmic_lbat_service {
|
||
|
|
compatible = "mediatek,mt6359-lbat_service";
|
||
|
|
};
|
||
|
|
|
||
|
|
mt6359_debug{
|
||
|
|
compatible = "mediatek,mt63xx-debug";
|
||
|
|
};
|
||
|
|
|
||
|
|
mt63xx-oc-debug {
|
||
|
|
compatible = "mediatek,mt63xx-oc-debug";
|
||
|
|
};
|
||
|
|
|
||
|
|
mt6359regulator: mt6359regulator {
|
||
|
|
compatible = "mediatek,mt6359-regulator";
|
||
|
|
mt_pmic_vs1_buck_reg: buck_vs1 {
|
||
|
|
regulator-name = "vs1";
|
||
|
|
regulator-min-microvolt = <800000>;
|
||
|
|
regulator-max-microvolt = <2200000>;
|
||
|
|
regulator-enable-ramp-delay = <0>;
|
||
|
|
};
|
||
|
|
mt_pmic_vgpu11_buck_reg: buck_vgpu11 {
|
||
|
|
regulator-name = "vgpu11";
|
||
|
|
regulator-min-microvolt = <400000>;
|
||
|
|
regulator-max-microvolt = <1193750>;
|
||
|
|
regulator-ramp-delay = <5000>;
|
||
|
|
regulator-enable-ramp-delay = <200>;
|
||
|
|
regulator-allowed-modes = <0 1 2>;
|
||
|
|
};
|
||
|
|
mt_pmic_vmodem_buck_reg: buck_vmodem {
|
||
|
|
regulator-name = "vmodem";
|
||
|
|
regulator-min-microvolt = <400000>;
|
||
|
|
regulator-max-microvolt = <1100000>;
|
||
|
|
regulator-ramp-delay = <10760>;
|
||
|
|
regulator-enable-ramp-delay = <200>;
|
||
|
|
};
|
||
|
|
mt_pmic_vpu_buck_reg: buck_vpu {
|
||
|
|
regulator-name = "vpu";
|
||
|
|
regulator-min-microvolt = <400000>;
|
||
|
|
regulator-max-microvolt = <1193750>;
|
||
|
|
regulator-ramp-delay = <5000>;
|
||
|
|
regulator-enable-ramp-delay = <200>;
|
||
|
|
regulator-allowed-modes = <0 1 2>;
|
||
|
|
};
|
||
|
|
mt_pmic_vcore_buck_reg: buck_vcore {
|
||
|
|
regulator-name = "vcore";
|
||
|
|
regulator-min-microvolt = <400000>;
|
||
|
|
regulator-max-microvolt = <1193750>;
|
||
|
|
regulator-ramp-delay = <5000>;
|
||
|
|
regulator-enable-ramp-delay = <200>;
|
||
|
|
regulator-allowed-modes = <0 1 2>;
|
||
|
|
};
|
||
|
|
mt_pmic_vs2_buck_reg: buck_vs2 {
|
||
|
|
regulator-name = "vs2";
|
||
|
|
regulator-min-microvolt = <800000>;
|
||
|
|
regulator-max-microvolt = <1600000>;
|
||
|
|
regulator-enable-ramp-delay = <0>;
|
||
|
|
};
|
||
|
|
mt_pmic_vpa_buck_reg: buck_vpa {
|
||
|
|
regulator-name = "vpa";
|
||
|
|
regulator-min-microvolt = <500000>;
|
||
|
|
regulator-max-microvolt = <3650000>;
|
||
|
|
regulator-enable-ramp-delay = <300>;
|
||
|
|
};
|
||
|
|
mt_pmic_vproc2_buck_reg: buck_vproc2 {
|
||
|
|
regulator-name = "vproc2";
|
||
|
|
regulator-min-microvolt = <400000>;
|
||
|
|
regulator-max-microvolt = <1193750>;
|
||
|
|
regulator-ramp-delay = <7500>;
|
||
|
|
regulator-enable-ramp-delay = <200>;
|
||
|
|
regulator-allowed-modes = <0 1 2>;
|
||
|
|
};
|
||
|
|
mt_pmic_vproc1_buck_reg: buck_vproc1 {
|
||
|
|
regulator-name = "vproc1";
|
||
|
|
regulator-min-microvolt = <400000>;
|
||
|
|
regulator-max-microvolt = <1193750>;
|
||
|
|
regulator-ramp-delay = <7500>;
|
||
|
|
regulator-enable-ramp-delay = <200>;
|
||
|
|
regulator-allowed-modes = <0 1 2>;
|
||
|
|
};
|
||
|
|
mt_pmic_vcore_sshub_buck_reg: buck_vcore_sshub {
|
||
|
|
regulator-name = "vcore_sshub";
|
||
|
|
regulator-min-microvolt = <400000>;
|
||
|
|
regulator-max-microvolt = <1193750>;
|
||
|
|
};
|
||
|
|
mt_pmic_vaud18_ldo_reg: ldo_vaud18 {
|
||
|
|
regulator-name = "vaud18";
|
||
|
|
regulator-min-microvolt = <1800000>;
|
||
|
|
regulator-max-microvolt = <1800000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vsim1_ldo_reg: ldo_vsim1 {
|
||
|
|
regulator-name = "vsim1";
|
||
|
|
regulator-min-microvolt = <1700000>;
|
||
|
|
regulator-max-microvolt = <3100000>;
|
||
|
|
regulator-enable-ramp-delay = <480>;
|
||
|
|
};
|
||
|
|
mt_pmic_vibr_ldo_reg: ldo_vibr {
|
||
|
|
regulator-name = "vibr";
|
||
|
|
regulator-min-microvolt = <1200000>;
|
||
|
|
regulator-max-microvolt = <3300000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vrf12_ldo_reg: ldo_vrf12 {
|
||
|
|
regulator-name = "vrf12";
|
||
|
|
regulator-min-microvolt = <1100000>;
|
||
|
|
regulator-max-microvolt = <1300000>;
|
||
|
|
regulator-enable-ramp-delay = <120>;
|
||
|
|
};
|
||
|
|
mt_pmic_vusb_ldo_reg: ldo_vusb {
|
||
|
|
regulator-name = "vusb";
|
||
|
|
regulator-min-microvolt = <3000000>;
|
||
|
|
regulator-max-microvolt = <3000000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vsram_proc2_ldo_reg: ldo_vsram_proc2 {
|
||
|
|
regulator-name = "vsram_proc2";
|
||
|
|
regulator-min-microvolt = <500000>;
|
||
|
|
regulator-max-microvolt = <1193750>;
|
||
|
|
regulator-ramp-delay = <7500>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vio18_ldo_reg: ldo_vio18 {
|
||
|
|
regulator-name = "vio18";
|
||
|
|
regulator-min-microvolt = <1700000>;
|
||
|
|
regulator-max-microvolt = <1900000>;
|
||
|
|
regulator-enable-ramp-delay = <960>;
|
||
|
|
};
|
||
|
|
mt_pmic_vcamio_ldo_reg: ldo_vcamio {
|
||
|
|
regulator-name = "vcamio";
|
||
|
|
regulator-min-microvolt = <1700000>;
|
||
|
|
regulator-max-microvolt = <1900000>;
|
||
|
|
regulator-enable-ramp-delay = <1920>;
|
||
|
|
};
|
||
|
|
mt_pmic_vcn18_ldo_reg: ldo_vcn18 {
|
||
|
|
regulator-name = "vcn18";
|
||
|
|
regulator-min-microvolt = <1800000>;
|
||
|
|
regulator-max-microvolt = <1800000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vfe28_ldo_reg: ldo_vfe28 {
|
||
|
|
regulator-name = "vfe28";
|
||
|
|
regulator-min-microvolt = <2800000>;
|
||
|
|
regulator-max-microvolt = <2800000>;
|
||
|
|
regulator-enable-ramp-delay = <120>;
|
||
|
|
};
|
||
|
|
mt_pmic_vcn13_ldo_reg: ldo_vcn13 {
|
||
|
|
regulator-name = "vcn13";
|
||
|
|
regulator-min-microvolt = <900000>;
|
||
|
|
regulator-max-microvolt = <1300000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt {
|
||
|
|
regulator-name = "vcn33_1_bt";
|
||
|
|
regulator-min-microvolt = <2800000>;
|
||
|
|
regulator-max-microvolt = <3500000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi {
|
||
|
|
regulator-name = "vcn33_1_wifi";
|
||
|
|
regulator-min-microvolt = <2800000>;
|
||
|
|
regulator-max-microvolt = <3500000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vaux18_ldo_reg: ldo_vaux18 {
|
||
|
|
regulator-name = "vaux18";
|
||
|
|
regulator-min-microvolt = <1800000>;
|
||
|
|
regulator-max-microvolt = <1800000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vsram_others_ldo_reg: ldo_vsram_others {
|
||
|
|
regulator-name = "vsram_others";
|
||
|
|
regulator-min-microvolt = <500000>;
|
||
|
|
regulator-max-microvolt = <1193750>;
|
||
|
|
regulator-ramp-delay = <5000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vefuse_ldo_reg: ldo_vefuse {
|
||
|
|
regulator-name = "vefuse";
|
||
|
|
regulator-min-microvolt = <1700000>;
|
||
|
|
regulator-max-microvolt = <2000000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vxo22_ldo_reg: ldo_vxo22 {
|
||
|
|
regulator-name = "vxo22";
|
||
|
|
regulator-min-microvolt = <1800000>;
|
||
|
|
regulator-max-microvolt = <2200000>;
|
||
|
|
regulator-enable-ramp-delay = <120>;
|
||
|
|
};
|
||
|
|
mt_pmic_vrfck_ldo_reg: ldo_vrfck {
|
||
|
|
regulator-name = "vrfck";
|
||
|
|
regulator-min-microvolt = <1500000>;
|
||
|
|
regulator-max-microvolt = <1700000>;
|
||
|
|
regulator-enable-ramp-delay = <480>;
|
||
|
|
};
|
||
|
|
mt_pmic_vbif28_ldo_reg: ldo_vbif28 {
|
||
|
|
regulator-name = "vbif28";
|
||
|
|
regulator-min-microvolt = <2800000>;
|
||
|
|
regulator-max-microvolt = <2800000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vio28_ldo_reg: ldo_vio28 {
|
||
|
|
regulator-name = "vio28";
|
||
|
|
regulator-min-microvolt = <2800000>;
|
||
|
|
regulator-max-microvolt = <3300000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vemc_ldo_reg: ldo_vemc {
|
||
|
|
regulator-name = "vemc";
|
||
|
|
regulator-min-microvolt = <2900000>;
|
||
|
|
regulator-max-microvolt = <3300000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt {
|
||
|
|
regulator-name = "vcn33_2_bt";
|
||
|
|
regulator-min-microvolt = <2800000>;
|
||
|
|
regulator-max-microvolt = <3500000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi {
|
||
|
|
regulator-name = "vcn33_2_wifi";
|
||
|
|
regulator-min-microvolt = <2800000>;
|
||
|
|
regulator-max-microvolt = <3500000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_va12_ldo_reg: ldo_va12 {
|
||
|
|
regulator-name = "va12";
|
||
|
|
regulator-min-microvolt = <1200000>;
|
||
|
|
regulator-max-microvolt = <1300000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_va09_ldo_reg: ldo_va09 {
|
||
|
|
regulator-name = "va09";
|
||
|
|
regulator-min-microvolt = <800000>;
|
||
|
|
regulator-max-microvolt = <1200000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vrf18_ldo_reg: ldo_vrf18 {
|
||
|
|
regulator-name = "vrf18";
|
||
|
|
regulator-min-microvolt = <1700000>;
|
||
|
|
regulator-max-microvolt = <1810000>;
|
||
|
|
regulator-enable-ramp-delay = <120>;
|
||
|
|
};
|
||
|
|
mt_pmic_vsram_md_ldo_reg: ldo_vsram_md {
|
||
|
|
regulator-name = "vsram_md";
|
||
|
|
regulator-min-microvolt = <500000>;
|
||
|
|
regulator-max-microvolt = <1100000>;
|
||
|
|
regulator-ramp-delay = <10760>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vufs_ldo_reg: ldo_vufs {
|
||
|
|
regulator-name = "vufs";
|
||
|
|
regulator-min-microvolt = <1700000>;
|
||
|
|
regulator-max-microvolt = <1900000>;
|
||
|
|
regulator-enable-ramp-delay = <1920>;
|
||
|
|
regulator-allowed-modes = <0 1>;
|
||
|
|
};
|
||
|
|
mt_pmic_vm18_ldo_reg: ldo_vm18 {
|
||
|
|
regulator-name = "vm18";
|
||
|
|
regulator-min-microvolt = <1700000>;
|
||
|
|
regulator-max-microvolt = <1900000>;
|
||
|
|
regulator-enable-ramp-delay = <1920>;
|
||
|
|
};
|
||
|
|
mt_pmic_vbbck_ldo_reg: ldo_vbbck {
|
||
|
|
regulator-name = "vbbck";
|
||
|
|
regulator-min-microvolt = <1100000>;
|
||
|
|
regulator-max-microvolt = <1200000>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vsram_proc1_ldo_reg: ldo_vsram_proc1 {
|
||
|
|
regulator-name = "vsram_proc1";
|
||
|
|
regulator-min-microvolt = <500000>;
|
||
|
|
regulator-max-microvolt = <1193750>;
|
||
|
|
regulator-ramp-delay = <7500>;
|
||
|
|
regulator-enable-ramp-delay = <240>;
|
||
|
|
};
|
||
|
|
mt_pmic_vsim2_ldo_reg: ldo_vsim2 {
|
||
|
|
regulator-name = "vsim2";
|
||
|
|
regulator-min-microvolt = <1700000>;
|
||
|
|
regulator-max-microvolt = <3100000>;
|
||
|
|
regulator-enable-ramp-delay = <480>;
|
||
|
|
};
|
||
|
|
mt_pmic_vsram_others_sshub_ldo_reg:
|
||
|
|
ldo_vsram_others_sshub {
|
||
|
|
regulator-name = "vsram_others_sshub";
|
||
|
|
regulator-min-microvolt = <500000>;
|
||
|
|
regulator-max-microvolt = <1193750>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
mtk_rtc: mtk_rtc {
|
||
|
|
compatible = "mediatek,mt6359-rtc";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <1>;
|
||
|
|
bootmode = <&chosen>;
|
||
|
|
|
||
|
|
fg_init: fg_init {
|
||
|
|
reg = <0 0x1>;
|
||
|
|
bits = <0 8>;
|
||
|
|
};
|
||
|
|
fg_soc: fg_soc {
|
||
|
|
reg = <1 0x1>;
|
||
|
|
bits = <0 8>;
|
||
|
|
};
|
||
|
|
ext_32k: ext_32k {
|
||
|
|
reg = <2 0x1>;
|
||
|
|
bits = <6 1>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
clock_buffer_ctrl: clock_buffer_ctrl {
|
||
|
|
compatible = "mediatek,clock_buffer";
|
||
|
|
n-clkbuf-pmic-dependent = <7>;
|
||
|
|
clkbuf-pmic-dependent = "pmic-bblplm-hw",
|
||
|
|
"pmic-bblpm-sel",
|
||
|
|
"pmic-ldo-vrfck",
|
||
|
|
"pmic-ldo-vbbck",
|
||
|
|
"pmic-auxout-sel",
|
||
|
|
"pmic-auxout-xo",
|
||
|
|
"pmic-auxout-bblpm-en";
|
||
|
|
|
||
|
|
pmic-dcxo-cw = <0x788>;
|
||
|
|
pmic-xo-mode = <0x788 0 0x788 3 0x788 6 0x788 9
|
||
|
|
0xffff 0xffff 0x79e 9 0x79e 12>;
|
||
|
|
pmic-xo-en = <0x788 2 0x788 5 0x788 8 0x788 11
|
||
|
|
0xffff 0xffff 0x79e 11 0x79e 14>;
|
||
|
|
pmic-bblpm-sw = <0x788 12>;
|
||
|
|
pmic-srclkeni3 = <0x458 0>;
|
||
|
|
|
||
|
|
n-pmic-bblplm-hw = <7>;
|
||
|
|
pmic-bblplm-hw = <0x7a8 1 0x7a8 2 0x7a8 3 0x7a8 4
|
||
|
|
0xffff 0xffff 0x7a8 5 0x7a8 6>;
|
||
|
|
n-pmic-bblpm-sel = <1>;
|
||
|
|
pmic-bblpm-sel = <0x7a8 0>;
|
||
|
|
n-pmic-ldo-vrfck = <2>;
|
||
|
|
pmic-ldo-vrfck = <0x1d1a 0 0x1d1e 14>;
|
||
|
|
n-pmic-ldo-vbbck = <2>;
|
||
|
|
pmic-ldo-vbbck = <0x1d2a 0 0x1d2e 14>;
|
||
|
|
n-pmic-auxout-sel = <4>;
|
||
|
|
pmic-auxout-sel = <0x7b0 0 0x7b0 6 0x7b0 27 0x7b0 39>;
|
||
|
|
n-pmic-auxout-xo = <7>;
|
||
|
|
pmic-auxout-xo = <0x7b2 13 0x7b2 11 0x7b2 9 0x7b2 7
|
||
|
|
0xffff 0xffff 0x7b2 5 0x7b2 3>;
|
||
|
|
n-pmic-auxout-bblpm-en = <1>;
|
||
|
|
pmic-auxout-bblpm-en = <0x7b2 0>;
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
mt6359_misc: mt6359_misc {
|
||
|
|
compatible = "mediatek,mt6359-misc";
|
||
|
|
base = <0x580>;
|
||
|
|
apply-lpsd-solution;
|
||
|
|
dcxo-switch;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|