366 lines
12 KiB
C
366 lines
12 KiB
C
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/*
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* Copyright (c) 2003-2012 Broadcom Corporation
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* All Rights Reserved
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the Broadcom
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* license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _NLM_FMN_H_
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#define _NLM_FMN_H_
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#include <asm/netlogic/mips-extns.h> /* for COP2 access */
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/* Station IDs */
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#define FMN_STNID_CPU0 0x00
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#define FMN_STNID_CPU1 0x08
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#define FMN_STNID_CPU2 0x10
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#define FMN_STNID_CPU3 0x18
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#define FMN_STNID_CPU4 0x20
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#define FMN_STNID_CPU5 0x28
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#define FMN_STNID_CPU6 0x30
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#define FMN_STNID_CPU7 0x38
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#define FMN_STNID_XGS0_TX 64
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#define FMN_STNID_XMAC0_00_TX 64
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#define FMN_STNID_XMAC0_01_TX 65
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#define FMN_STNID_XMAC0_02_TX 66
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#define FMN_STNID_XMAC0_03_TX 67
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#define FMN_STNID_XMAC0_04_TX 68
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#define FMN_STNID_XMAC0_05_TX 69
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#define FMN_STNID_XMAC0_06_TX 70
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#define FMN_STNID_XMAC0_07_TX 71
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#define FMN_STNID_XMAC0_08_TX 72
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#define FMN_STNID_XMAC0_09_TX 73
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#define FMN_STNID_XMAC0_10_TX 74
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#define FMN_STNID_XMAC0_11_TX 75
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#define FMN_STNID_XMAC0_12_TX 76
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#define FMN_STNID_XMAC0_13_TX 77
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#define FMN_STNID_XMAC0_14_TX 78
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#define FMN_STNID_XMAC0_15_TX 79
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#define FMN_STNID_XGS1_TX 80
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#define FMN_STNID_XMAC1_00_TX 80
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#define FMN_STNID_XMAC1_01_TX 81
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#define FMN_STNID_XMAC1_02_TX 82
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#define FMN_STNID_XMAC1_03_TX 83
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#define FMN_STNID_XMAC1_04_TX 84
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#define FMN_STNID_XMAC1_05_TX 85
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#define FMN_STNID_XMAC1_06_TX 86
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#define FMN_STNID_XMAC1_07_TX 87
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#define FMN_STNID_XMAC1_08_TX 88
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#define FMN_STNID_XMAC1_09_TX 89
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#define FMN_STNID_XMAC1_10_TX 90
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#define FMN_STNID_XMAC1_11_TX 91
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#define FMN_STNID_XMAC1_12_TX 92
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#define FMN_STNID_XMAC1_13_TX 93
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#define FMN_STNID_XMAC1_14_TX 94
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#define FMN_STNID_XMAC1_15_TX 95
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#define FMN_STNID_GMAC 96
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#define FMN_STNID_GMACJFR_0 96
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#define FMN_STNID_GMACRFR_0 97
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#define FMN_STNID_GMACTX0 98
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#define FMN_STNID_GMACTX1 99
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#define FMN_STNID_GMACTX2 100
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#define FMN_STNID_GMACTX3 101
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#define FMN_STNID_GMACJFR_1 102
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#define FMN_STNID_GMACRFR_1 103
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#define FMN_STNID_DMA 104
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#define FMN_STNID_DMA_0 104
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#define FMN_STNID_DMA_1 105
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#define FMN_STNID_DMA_2 106
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#define FMN_STNID_DMA_3 107
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#define FMN_STNID_XGS0FR 112
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#define FMN_STNID_XMAC0JFR 112
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#define FMN_STNID_XMAC0RFR 113
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#define FMN_STNID_XGS1FR 114
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#define FMN_STNID_XMAC1JFR 114
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#define FMN_STNID_XMAC1RFR 115
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#define FMN_STNID_SEC 120
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#define FMN_STNID_SEC0 120
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#define FMN_STNID_SEC1 121
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#define FMN_STNID_SEC2 122
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#define FMN_STNID_SEC3 123
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#define FMN_STNID_PK0 124
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#define FMN_STNID_SEC_RSA 124
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#define FMN_STNID_SEC_RSVD0 125
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#define FMN_STNID_SEC_RSVD1 126
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#define FMN_STNID_SEC_RSVD2 127
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#define FMN_STNID_GMAC1 80
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#define FMN_STNID_GMAC1_FR_0 81
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#define FMN_STNID_GMAC1_TX0 82
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#define FMN_STNID_GMAC1_TX1 83
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#define FMN_STNID_GMAC1_TX2 84
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#define FMN_STNID_GMAC1_TX3 85
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#define FMN_STNID_GMAC1_FR_1 87
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#define FMN_STNID_GMAC0 96
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#define FMN_STNID_GMAC0_FR_0 97
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#define FMN_STNID_GMAC0_TX0 98
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#define FMN_STNID_GMAC0_TX1 99
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#define FMN_STNID_GMAC0_TX2 100
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#define FMN_STNID_GMAC0_TX3 101
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#define FMN_STNID_GMAC0_FR_1 103
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#define FMN_STNID_CMP_0 108
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#define FMN_STNID_CMP_1 109
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#define FMN_STNID_CMP_2 110
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#define FMN_STNID_CMP_3 111
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#define FMN_STNID_PCIE_0 116
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#define FMN_STNID_PCIE_1 117
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#define FMN_STNID_PCIE_2 118
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#define FMN_STNID_PCIE_3 119
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#define FMN_STNID_XLS_PK0 121
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#define nlm_read_c2_cc0(s) __read_32bit_c2_register($16, s)
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#define nlm_read_c2_cc1(s) __read_32bit_c2_register($17, s)
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#define nlm_read_c2_cc2(s) __read_32bit_c2_register($18, s)
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#define nlm_read_c2_cc3(s) __read_32bit_c2_register($19, s)
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#define nlm_read_c2_cc4(s) __read_32bit_c2_register($20, s)
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#define nlm_read_c2_cc5(s) __read_32bit_c2_register($21, s)
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#define nlm_read_c2_cc6(s) __read_32bit_c2_register($22, s)
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#define nlm_read_c2_cc7(s) __read_32bit_c2_register($23, s)
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#define nlm_read_c2_cc8(s) __read_32bit_c2_register($24, s)
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#define nlm_read_c2_cc9(s) __read_32bit_c2_register($25, s)
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#define nlm_read_c2_cc10(s) __read_32bit_c2_register($26, s)
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#define nlm_read_c2_cc11(s) __read_32bit_c2_register($27, s)
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#define nlm_read_c2_cc12(s) __read_32bit_c2_register($28, s)
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#define nlm_read_c2_cc13(s) __read_32bit_c2_register($29, s)
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#define nlm_read_c2_cc14(s) __read_32bit_c2_register($30, s)
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#define nlm_read_c2_cc15(s) __read_32bit_c2_register($31, s)
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#define nlm_write_c2_cc0(s, v) __write_32bit_c2_register($16, s, v)
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#define nlm_write_c2_cc1(s, v) __write_32bit_c2_register($17, s, v)
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#define nlm_write_c2_cc2(s, v) __write_32bit_c2_register($18, s, v)
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#define nlm_write_c2_cc3(s, v) __write_32bit_c2_register($19, s, v)
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#define nlm_write_c2_cc4(s, v) __write_32bit_c2_register($20, s, v)
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#define nlm_write_c2_cc5(s, v) __write_32bit_c2_register($21, s, v)
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#define nlm_write_c2_cc6(s, v) __write_32bit_c2_register($22, s, v)
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#define nlm_write_c2_cc7(s, v) __write_32bit_c2_register($23, s, v)
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#define nlm_write_c2_cc8(s, v) __write_32bit_c2_register($24, s, v)
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#define nlm_write_c2_cc9(s, v) __write_32bit_c2_register($25, s, v)
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#define nlm_write_c2_cc10(s, v) __write_32bit_c2_register($26, s, v)
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#define nlm_write_c2_cc11(s, v) __write_32bit_c2_register($27, s, v)
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#define nlm_write_c2_cc12(s, v) __write_32bit_c2_register($28, s, v)
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#define nlm_write_c2_cc13(s, v) __write_32bit_c2_register($29, s, v)
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#define nlm_write_c2_cc14(s, v) __write_32bit_c2_register($30, s, v)
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#define nlm_write_c2_cc15(s, v) __write_32bit_c2_register($31, s, v)
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#define nlm_read_c2_status0() __read_32bit_c2_register($2, 0)
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#define nlm_write_c2_status0(v) __write_32bit_c2_register($2, 0, v)
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#define nlm_read_c2_status1() __read_32bit_c2_register($2, 1)
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#define nlm_write_c2_status1(v) __write_32bit_c2_register($2, 1, v)
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#define nlm_read_c2_status(sel) __read_32bit_c2_register($2, 0)
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#define nlm_read_c2_config() __read_32bit_c2_register($3, 0)
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#define nlm_write_c2_config(v) __write_32bit_c2_register($3, 0, v)
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#define nlm_read_c2_bucksize(b) __read_32bit_c2_register($4, b)
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#define nlm_write_c2_bucksize(b, v) __write_32bit_c2_register($4, b, v)
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#define nlm_read_c2_rx_msg0() __read_64bit_c2_register($1, 0)
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#define nlm_read_c2_rx_msg1() __read_64bit_c2_register($1, 1)
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#define nlm_read_c2_rx_msg2() __read_64bit_c2_register($1, 2)
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#define nlm_read_c2_rx_msg3() __read_64bit_c2_register($1, 3)
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#define nlm_write_c2_tx_msg0(v) __write_64bit_c2_register($0, 0, v)
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#define nlm_write_c2_tx_msg1(v) __write_64bit_c2_register($0, 1, v)
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#define nlm_write_c2_tx_msg2(v) __write_64bit_c2_register($0, 2, v)
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#define nlm_write_c2_tx_msg3(v) __write_64bit_c2_register($0, 3, v)
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#define FMN_STN_RX_QSIZE 256
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#define FMN_NSTATIONS 128
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#define FMN_CORE_NBUCKETS 8
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static inline void nlm_msgsnd(unsigned int stid)
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{
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__asm__ volatile (
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".set push\n"
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".set noreorder\n"
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".set noat\n"
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"move $1, %0\n"
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"c2 0x10001\n" /* msgsnd $1 */
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".set pop\n"
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: : "r" (stid) : "$1"
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);
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}
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static inline void nlm_msgld(unsigned int pri)
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{
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__asm__ volatile (
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".set push\n"
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".set noreorder\n"
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".set noat\n"
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"move $1, %0\n"
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"c2 0x10002\n" /* msgld $1 */
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".set pop\n"
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: : "r" (pri) : "$1"
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);
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}
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static inline void nlm_msgwait(unsigned int mask)
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{
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__asm__ volatile (
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".set push\n"
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".set noreorder\n"
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".set noat\n"
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"move $8, %0\n"
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"c2 0x10003\n" /* msgwait $1 */
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".set pop\n"
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: : "r" (mask) : "$1"
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);
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}
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/*
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* Disable interrupts and enable COP2 access
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*/
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static inline uint32_t nlm_cop2_enable_irqsave(void)
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{
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uint32_t sr = read_c0_status();
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write_c0_status((sr & ~ST0_IE) | ST0_CU2);
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return sr;
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}
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static inline void nlm_cop2_disable_irqrestore(uint32_t sr)
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{
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write_c0_status(sr);
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}
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static inline void nlm_fmn_setup_intr(int irq, unsigned int tmask)
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{
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uint32_t config;
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config = (1 << 24) /* interrupt water mark - 1 msg */
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| (irq << 16) /* irq */
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| (tmask << 8) /* thread mask */
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| 0x2; /* enable watermark intr, disable empty intr */
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nlm_write_c2_config(config);
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}
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struct nlm_fmn_msg {
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uint64_t msg0;
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uint64_t msg1;
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uint64_t msg2;
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uint64_t msg3;
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};
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static inline int nlm_fmn_send(unsigned int size, unsigned int code,
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unsigned int stid, struct nlm_fmn_msg *msg)
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{
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unsigned int dest;
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uint32_t status;
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int i;
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/*
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* Make sure that all the writes pending at the cpu are flushed.
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* Any writes pending on CPU will not be see by devices. L1/L2
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* caches are coherent with IO, so no cache flush needed.
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*/
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__asm __volatile("sync");
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/* Load TX message buffers */
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nlm_write_c2_tx_msg0(msg->msg0);
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nlm_write_c2_tx_msg1(msg->msg1);
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nlm_write_c2_tx_msg2(msg->msg2);
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nlm_write_c2_tx_msg3(msg->msg3);
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dest = ((size - 1) << 16) | (code << 8) | stid;
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||
|
|
|
||
|
|
/*
|
||
|
|
* Retry a few times on credit fail, this should be a
|
||
|
|
* transient condition, unless there is a configuration
|
||
|
|
* failure, or the receiver is stuck.
|
||
|
|
*/
|
||
|
|
for (i = 0; i < 8; i++) {
|
||
|
|
nlm_msgsnd(dest);
|
||
|
|
status = nlm_read_c2_status0();
|
||
|
|
if ((status & 0x4) == 0)
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* If there is a credit failure, return error */
|
||
|
|
return status & 0x06;
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline int nlm_fmn_receive(int bucket, int *size, int *code, int *stid,
|
||
|
|
struct nlm_fmn_msg *msg)
|
||
|
|
{
|
||
|
|
uint32_t status, tmp;
|
||
|
|
|
||
|
|
nlm_msgld(bucket);
|
||
|
|
|
||
|
|
/* wait for load pending to clear */
|
||
|
|
do {
|
||
|
|
status = nlm_read_c2_status0();
|
||
|
|
} while ((status & 0x08) != 0);
|
||
|
|
|
||
|
|
/* receive error bits */
|
||
|
|
tmp = status & 0x30;
|
||
|
|
if (tmp != 0)
|
||
|
|
return tmp;
|
||
|
|
|
||
|
|
*size = ((status & 0xc0) >> 6) + 1;
|
||
|
|
*code = (status & 0xff00) >> 8;
|
||
|
|
*stid = (status & 0x7f0000) >> 16;
|
||
|
|
msg->msg0 = nlm_read_c2_rx_msg0();
|
||
|
|
msg->msg1 = nlm_read_c2_rx_msg1();
|
||
|
|
msg->msg2 = nlm_read_c2_rx_msg2();
|
||
|
|
msg->msg3 = nlm_read_c2_rx_msg3();
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
struct xlr_fmn_info {
|
||
|
|
int num_buckets;
|
||
|
|
int start_stn_id;
|
||
|
|
int end_stn_id;
|
||
|
|
int credit_config[128];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct xlr_board_fmn_config {
|
||
|
|
int bucket_size[128]; /* size of buckets for all stations */
|
||
|
|
struct xlr_fmn_info cpu[8];
|
||
|
|
struct xlr_fmn_info gmac[2];
|
||
|
|
struct xlr_fmn_info dma;
|
||
|
|
struct xlr_fmn_info cmp;
|
||
|
|
struct xlr_fmn_info sae;
|
||
|
|
struct xlr_fmn_info xgmac[2];
|
||
|
|
};
|
||
|
|
|
||
|
|
extern int nlm_register_fmn_handler(int start, int end,
|
||
|
|
void (*fn)(int, int, int, int, struct nlm_fmn_msg *, void *),
|
||
|
|
void *arg);
|
||
|
|
extern void xlr_percpu_fmn_init(void);
|
||
|
|
extern void nlm_setup_fmn_irq(void);
|
||
|
|
extern void xlr_board_info_setup(void);
|
||
|
|
|
||
|
|
extern struct xlr_board_fmn_config xlr_board_fmn_config;
|
||
|
|
#endif
|