87 lines
3.3 KiB
C
87 lines
3.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _PARISC_SUPERIO_H
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#define _PARISC_SUPERIO_H
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#define IC_PIC1 0x20 /* PCI I/O address of master 8259 */
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#define IC_PIC2 0xA0 /* PCI I/O address of slave */
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/* Config Space Offsets to configuration and base address registers */
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#define SIO_CR 0x5A /* Configuration Register */
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#define SIO_ACPIBAR 0x88 /* ACPI BAR */
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#define SIO_FDCBAR 0x90 /* Floppy Disk Controller BAR */
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#define SIO_SP1BAR 0x94 /* Serial 1 BAR */
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#define SIO_SP2BAR 0x98 /* Serial 2 BAR */
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#define SIO_PPBAR 0x9C /* Parallel BAR */
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#define TRIGGER_1 0x67 /* Edge/level trigger register 1 */
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#define TRIGGER_2 0x68 /* Edge/level trigger register 2 */
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/* Interrupt Routing Control registers */
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#define CFG_IR_SER 0x69 /* Serial 1 [0:3] and Serial 2 [4:7] */
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#define CFG_IR_PFD 0x6a /* Parallel [0:3] and Floppy [4:7] */
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#define CFG_IR_IDE 0x6b /* IDE1 [0:3] and IDE2 [4:7] */
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#define CFG_IR_INTAB 0x6c /* PCI INTA [0:3] and INT B [4:7] */
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#define CFG_IR_INTCD 0x6d /* PCI INTC [0:3] and INT D [4:7] */
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#define CFG_IR_PS2 0x6e /* PS/2 KBINT [0:3] and Mouse [4:7] */
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#define CFG_IR_FXBUS 0x6f /* FXIRQ[0] [0:3] and FXIRQ[1] [4:7] */
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#define CFG_IR_USB 0x70 /* FXIRQ[2] [0:3] and USB [4:7] */
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#define CFG_IR_ACPI 0x71 /* ACPI SCI [0:3] and reserved [4:7] */
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#define CFG_IR_LOW CFG_IR_SER /* Lowest interrupt routing reg */
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#define CFG_IR_HIGH CFG_IR_ACPI /* Highest interrupt routing reg */
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/* 8259 operational control words */
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#define OCW2_EOI 0x20 /* Non-specific EOI */
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#define OCW2_SEOI 0x60 /* Specific EOI */
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#define OCW3_IIR 0x0A /* Read request register */
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#define OCW3_ISR 0x0B /* Read service register */
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#define OCW3_POLL 0x0C /* Poll the PIC for an interrupt vector */
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/* Interrupt lines. Only PIC1 is used */
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#define USB_IRQ 1 /* USB */
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#define SP1_IRQ 3 /* Serial port 1 */
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#define SP2_IRQ 4 /* Serial port 2 */
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#define PAR_IRQ 5 /* Parallel port */
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#define FDC_IRQ 6 /* Floppy controller */
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#define IDE_IRQ 7 /* IDE (pri+sec) */
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/* ACPI registers */
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#define USB_REG_CR 0x1f /* USB Regulator Control Register */
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#define SUPERIO_NIRQS 8
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struct superio_device {
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u32 fdc_base;
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u32 sp1_base;
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u32 sp2_base;
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u32 pp_base;
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u32 acpi_base;
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int suckyio_irq_enabled;
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struct pci_dev *lio_pdev; /* pci device for legacy IO (fn 1) */
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struct pci_dev *usb_pdev; /* pci device for USB (fn 2) */
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};
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/*
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* Does NS make a 87415 based plug in PCI card? If so, because of this
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* macro we currently don't support it being plugged into a machine
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* that contains a SuperIO chip AND has CONFIG_SUPERIO enabled.
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*
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* This could be fixed by checking to see if function 1 exists, and
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* if it is SuperIO Legacy IO; but really now, is this combination
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* going to EVER happen?
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*/
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#define SUPERIO_IDE_FN 0 /* Function number of IDE controller */
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#define SUPERIO_LIO_FN 1 /* Function number of Legacy IO controller */
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#define SUPERIO_USB_FN 2 /* Function number of USB controller */
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#define is_superio_device(x) \
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(((x)->vendor == PCI_VENDOR_ID_NS) && \
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( ((x)->device == PCI_DEVICE_ID_NS_87415) \
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|| ((x)->device == PCI_DEVICE_ID_NS_87560_LIO) \
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|| ((x)->device == PCI_DEVICE_ID_NS_87560_USB) ) )
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extern int superio_fixup_irq(struct pci_dev *pcidev); /* called by iosapic */
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#endif /* _PARISC_SUPERIO_H */
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