412 lines
11 KiB
C
412 lines
11 KiB
C
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/*
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* Low-Level PCI Support for the SH7780
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*
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* Copyright (C) 2005 - 2010 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/timer.h>
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#include <linux/irq.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/log2.h>
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#include "pci-sh4.h"
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#include <asm/mmu.h>
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#include <asm/sizes.h>
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#if defined(CONFIG_CPU_BIG_ENDIAN)
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# define PCICR_ENDIANNESS SH4_PCICR_BSWP
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#else
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# define PCICR_ENDIANNESS 0
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#endif
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static struct resource sh7785_pci_resources[] = {
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{
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.name = "PCI IO",
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.start = 0x1000,
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.end = SZ_4M - 1,
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.flags = IORESOURCE_IO,
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}, {
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.name = "PCI MEM 0",
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.start = 0xfd000000,
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.end = 0xfd000000 + SZ_16M - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.name = "PCI MEM 1",
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.start = 0x10000000,
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.end = 0x10000000 + SZ_64M - 1,
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.flags = IORESOURCE_MEM,
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}, {
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/*
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* 32-bit only resources must be last.
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*/
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.name = "PCI MEM 2",
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.start = 0xc0000000,
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.end = 0xc0000000 + SZ_512M - 1,
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.flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
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},
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};
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static struct pci_channel sh7780_pci_controller = {
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.pci_ops = &sh4_pci_ops,
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.resources = sh7785_pci_resources,
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.nr_resources = ARRAY_SIZE(sh7785_pci_resources),
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.io_offset = 0,
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.mem_offset = 0,
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.io_map_base = 0xfe200000,
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.serr_irq = evt2irq(0xa00),
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.err_irq = evt2irq(0xaa0),
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};
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struct pci_errors {
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unsigned int mask;
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const char *str;
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} pci_arbiter_errors[] = {
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{ SH4_PCIAINT_MBKN, "master broken" },
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{ SH4_PCIAINT_TBTO, "target bus time out" },
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{ SH4_PCIAINT_MBTO, "master bus time out" },
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{ SH4_PCIAINT_TABT, "target abort" },
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{ SH4_PCIAINT_MABT, "master abort" },
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{ SH4_PCIAINT_RDPE, "read data parity error" },
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{ SH4_PCIAINT_WDPE, "write data parity error" },
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}, pci_interrupt_errors[] = {
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{ SH4_PCIINT_MLCK, "master lock error" },
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{ SH4_PCIINT_TABT, "target-target abort" },
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{ SH4_PCIINT_TRET, "target retry time out" },
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{ SH4_PCIINT_MFDE, "master function disable error" },
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{ SH4_PCIINT_PRTY, "address parity error" },
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{ SH4_PCIINT_SERR, "SERR" },
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{ SH4_PCIINT_TWDP, "data parity error for target write" },
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{ SH4_PCIINT_TRDP, "PERR detected for target read" },
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{ SH4_PCIINT_MTABT, "target abort for master" },
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{ SH4_PCIINT_MMABT, "master abort for master" },
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{ SH4_PCIINT_MWPD, "master write data parity error" },
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{ SH4_PCIINT_MRPD, "master read data parity error" },
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};
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static irqreturn_t sh7780_pci_err_irq(int irq, void *dev_id)
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{
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struct pci_channel *hose = dev_id;
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unsigned long addr;
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unsigned int status;
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unsigned int cmd;
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int i;
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addr = __raw_readl(hose->reg_base + SH4_PCIALR);
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/*
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* Handle status errors.
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*/
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status = __raw_readw(hose->reg_base + PCI_STATUS);
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if (status & (PCI_STATUS_PARITY |
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PCI_STATUS_DETECTED_PARITY |
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PCI_STATUS_SIG_TARGET_ABORT |
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PCI_STATUS_REC_TARGET_ABORT |
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PCI_STATUS_REC_MASTER_ABORT)) {
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cmd = pcibios_handle_status_errors(addr, status, hose);
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if (likely(cmd))
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__raw_writew(cmd, hose->reg_base + PCI_STATUS);
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}
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/*
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* Handle arbiter errors.
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*/
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status = __raw_readl(hose->reg_base + SH4_PCIAINT);
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for (i = cmd = 0; i < ARRAY_SIZE(pci_arbiter_errors); i++) {
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if (status & pci_arbiter_errors[i].mask) {
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printk(KERN_DEBUG "PCI: %s, addr=%08lx\n",
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pci_arbiter_errors[i].str, addr);
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cmd |= pci_arbiter_errors[i].mask;
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}
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}
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__raw_writel(cmd, hose->reg_base + SH4_PCIAINT);
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/*
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* Handle the remaining PCI errors.
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*/
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status = __raw_readl(hose->reg_base + SH4_PCIINT);
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for (i = cmd = 0; i < ARRAY_SIZE(pci_interrupt_errors); i++) {
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if (status & pci_interrupt_errors[i].mask) {
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printk(KERN_DEBUG "PCI: %s, addr=%08lx\n",
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pci_interrupt_errors[i].str, addr);
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cmd |= pci_interrupt_errors[i].mask;
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}
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}
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__raw_writel(cmd, hose->reg_base + SH4_PCIINT);
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return IRQ_HANDLED;
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}
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static irqreturn_t sh7780_pci_serr_irq(int irq, void *dev_id)
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{
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struct pci_channel *hose = dev_id;
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printk(KERN_DEBUG "PCI: system error received: ");
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pcibios_report_status(PCI_STATUS_SIG_SYSTEM_ERROR, 1);
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printk("\n");
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/* Deassert SERR */
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__raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM);
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/* Back off the IRQ for awhile */
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disable_irq_nosync(irq);
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hose->serr_timer.expires = jiffies + HZ;
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add_timer(&hose->serr_timer);
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return IRQ_HANDLED;
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}
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static int __init sh7780_pci_setup_irqs(struct pci_channel *hose)
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{
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int ret;
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/* Clear out PCI arbiter IRQs */
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__raw_writel(0, hose->reg_base + SH4_PCIAINT);
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/* Clear all error conditions */
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__raw_writew(PCI_STATUS_DETECTED_PARITY | \
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PCI_STATUS_SIG_SYSTEM_ERROR | \
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PCI_STATUS_REC_MASTER_ABORT | \
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PCI_STATUS_REC_TARGET_ABORT | \
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PCI_STATUS_SIG_TARGET_ABORT | \
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PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS);
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ret = request_irq(hose->serr_irq, sh7780_pci_serr_irq, 0,
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"PCI SERR interrupt", hose);
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if (unlikely(ret)) {
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printk(KERN_ERR "PCI: Failed hooking SERR IRQ\n");
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return ret;
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}
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/*
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* The PCI ERR IRQ needs to be IRQF_SHARED since all of the power
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* down IRQ vectors are routed through the ERR IRQ vector. We
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* only request_irq() once as there is only a single masking
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* source for multiple events.
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*/
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ret = request_irq(hose->err_irq, sh7780_pci_err_irq, IRQF_SHARED,
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"PCI ERR interrupt", hose);
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if (unlikely(ret)) {
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free_irq(hose->serr_irq, hose);
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return ret;
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}
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/* Unmask all of the arbiter IRQs. */
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__raw_writel(SH4_PCIAINT_MBKN | SH4_PCIAINT_TBTO | SH4_PCIAINT_MBTO | \
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SH4_PCIAINT_TABT | SH4_PCIAINT_MABT | SH4_PCIAINT_RDPE | \
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SH4_PCIAINT_WDPE, hose->reg_base + SH4_PCIAINTM);
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/* Unmask all of the PCI IRQs */
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__raw_writel(SH4_PCIINTM_TTADIM | SH4_PCIINTM_TMTOIM | \
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SH4_PCIINTM_MDEIM | SH4_PCIINTM_APEDIM | \
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SH4_PCIINTM_SDIM | SH4_PCIINTM_DPEITWM | \
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SH4_PCIINTM_PEDITRM | SH4_PCIINTM_TADIMM | \
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SH4_PCIINTM_MADIMM | SH4_PCIINTM_MWPDIM | \
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SH4_PCIINTM_MRDPEIM, hose->reg_base + SH4_PCIINTM);
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return ret;
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}
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static inline void __init sh7780_pci_teardown_irqs(struct pci_channel *hose)
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{
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free_irq(hose->err_irq, hose);
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free_irq(hose->serr_irq, hose);
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}
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static void __init sh7780_pci66_init(struct pci_channel *hose)
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{
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unsigned int tmp;
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if (!pci_is_66mhz_capable(hose, 0, 0))
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return;
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/* Enable register access */
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tmp = __raw_readl(hose->reg_base + SH4_PCICR);
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tmp |= SH4_PCICR_PREFIX;
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__raw_writel(tmp, hose->reg_base + SH4_PCICR);
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/* Enable 66MHz operation */
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tmp = __raw_readw(hose->reg_base + PCI_STATUS);
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tmp |= PCI_STATUS_66MHZ;
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__raw_writew(tmp, hose->reg_base + PCI_STATUS);
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/* Done */
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tmp = __raw_readl(hose->reg_base + SH4_PCICR);
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tmp |= SH4_PCICR_PREFIX | SH4_PCICR_CFIN;
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__raw_writel(tmp, hose->reg_base + SH4_PCICR);
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}
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static int __init sh7780_pci_init(void)
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{
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struct pci_channel *chan = &sh7780_pci_controller;
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phys_addr_t memphys;
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size_t memsize;
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unsigned int id;
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const char *type;
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int ret, i;
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printk(KERN_NOTICE "PCI: Starting initialization.\n");
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chan->reg_base = 0xfe040000;
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/* Enable CPU access to the PCIC registers. */
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__raw_writel(PCIECR_ENBL, PCIECR);
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/* Reset */
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__raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_PRST | PCICR_ENDIANNESS,
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chan->reg_base + SH4_PCICR);
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/*
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* Wait for it to come back up. The spec says to allow for up to
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* 1 second after toggling the reset pin, but in practice 100ms
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* is more than enough.
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*/
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mdelay(100);
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id = __raw_readw(chan->reg_base + PCI_VENDOR_ID);
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if (id != PCI_VENDOR_ID_RENESAS) {
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printk(KERN_ERR "PCI: Unknown vendor ID 0x%04x.\n", id);
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return -ENODEV;
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}
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id = __raw_readw(chan->reg_base + PCI_DEVICE_ID);
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type = (id == PCI_DEVICE_ID_RENESAS_SH7763) ? "SH7763" :
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(id == PCI_DEVICE_ID_RENESAS_SH7780) ? "SH7780" :
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(id == PCI_DEVICE_ID_RENESAS_SH7781) ? "SH7781" :
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(id == PCI_DEVICE_ID_RENESAS_SH7785) ? "SH7785" :
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NULL;
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if (unlikely(!type)) {
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printk(KERN_ERR "PCI: Found an unsupported Renesas host "
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"controller, device id 0x%04x.\n", id);
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return -EINVAL;
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}
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printk(KERN_NOTICE "PCI: Found a Renesas %s host "
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"controller, revision %d.\n", type,
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__raw_readb(chan->reg_base + PCI_REVISION_ID));
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/*
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* Now throw it in to register initialization mode and
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* start the real work.
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*/
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__raw_writel(SH4_PCICR_PREFIX | PCICR_ENDIANNESS,
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chan->reg_base + SH4_PCICR);
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memphys = __pa(memory_start);
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memsize = roundup_pow_of_two(memory_end - memory_start);
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/*
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* If there's more than 512MB of memory, we need to roll over to
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* LAR1/LSR1.
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*/
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if (memsize > SZ_512M) {
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__raw_writel(memphys + SZ_512M, chan->reg_base + SH4_PCILAR1);
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__raw_writel((((memsize - SZ_512M) - SZ_1M) & 0x1ff00000) | 1,
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chan->reg_base + SH4_PCILSR1);
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memsize = SZ_512M;
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} else {
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/*
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* Otherwise just zero it out and disable it.
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*/
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__raw_writel(0, chan->reg_base + SH4_PCILAR1);
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__raw_writel(0, chan->reg_base + SH4_PCILSR1);
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}
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/*
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* LAR0/LSR0 covers up to the first 512MB, which is enough to
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* cover all of lowmem on most platforms.
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*/
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__raw_writel(memphys, chan->reg_base + SH4_PCILAR0);
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__raw_writel(((memsize - SZ_1M) & 0x1ff00000) | 1,
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chan->reg_base + SH4_PCILSR0);
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/*
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* Hook up the ERR and SERR IRQs.
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*/
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ret = sh7780_pci_setup_irqs(chan);
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if (unlikely(ret))
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return ret;
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/*
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* Disable the cache snoop controller for non-coherent DMA.
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*/
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__raw_writel(0, chan->reg_base + SH7780_PCICSCR0);
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__raw_writel(0, chan->reg_base + SH7780_PCICSAR0);
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__raw_writel(0, chan->reg_base + SH7780_PCICSCR1);
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__raw_writel(0, chan->reg_base + SH7780_PCICSAR1);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Setup the memory BARs
|
||
|
|
*/
|
||
|
|
for (i = 1; i < chan->nr_resources; i++) {
|
||
|
|
struct resource *res = chan->resources + i;
|
||
|
|
resource_size_t size;
|
||
|
|
|
||
|
|
if (unlikely(res->flags & IORESOURCE_IO))
|
||
|
|
continue;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Make sure we're in the right physical addressing mode
|
||
|
|
* for dealing with the resource.
|
||
|
|
*/
|
||
|
|
if ((res->flags & IORESOURCE_MEM_32BIT) && __in_29bit_mode()) {
|
||
|
|
chan->nr_resources--;
|
||
|
|
continue;
|
||
|
|
}
|
||
|
|
|
||
|
|
size = resource_size(res);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* The MBMR mask is calculated in units of 256kB, which
|
||
|
|
* keeps things pretty simple.
|
||
|
|
*/
|
||
|
|
__raw_writel(((roundup_pow_of_two(size) / SZ_256K) - 1) << 18,
|
||
|
|
chan->reg_base + SH7780_PCIMBMR(i - 1));
|
||
|
|
__raw_writel(res->start, chan->reg_base + SH7780_PCIMBR(i - 1));
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* And I/O.
|
||
|
|
*/
|
||
|
|
__raw_writel(0, chan->reg_base + PCI_BASE_ADDRESS_0);
|
||
|
|
__raw_writel(0, chan->reg_base + SH7780_PCIIOBR);
|
||
|
|
__raw_writel(0, chan->reg_base + SH7780_PCIIOBMR);
|
||
|
|
|
||
|
|
__raw_writew(PCI_COMMAND_SERR | PCI_COMMAND_WAIT | \
|
||
|
|
PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | \
|
||
|
|
PCI_COMMAND_MEMORY, chan->reg_base + PCI_COMMAND);
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Initialization mode complete, release the control register and
|
||
|
|
* enable round robin mode to stop device overruns/starvation.
|
||
|
|
*/
|
||
|
|
__raw_writel(SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO |
|
||
|
|
PCICR_ENDIANNESS,
|
||
|
|
chan->reg_base + SH4_PCICR);
|
||
|
|
|
||
|
|
ret = register_pci_controller(chan);
|
||
|
|
if (unlikely(ret))
|
||
|
|
goto err;
|
||
|
|
|
||
|
|
sh7780_pci66_init(chan);
|
||
|
|
|
||
|
|
printk(KERN_NOTICE "PCI: Running at %dMHz.\n",
|
||
|
|
(__raw_readw(chan->reg_base + PCI_STATUS) & PCI_STATUS_66MHZ) ?
|
||
|
|
66 : 33);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err:
|
||
|
|
sh7780_pci_teardown_irqs(chan);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
arch_initcall(sh7780_pci_init);
|