414 lines
12 KiB
C
414 lines
12 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_IO_H
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#define _ASM_X86_IO_H
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/*
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* This file contains the definitions for the x86 IO instructions
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* inb/inw/inl/outb/outw/outl and the "string versions" of the same
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* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
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* versions of the single-IO instructions (inb_p/inw_p/..).
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*
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* This file is not meant to be obfuscating: it's just complicated
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* to (a) handle it all in a way that makes gcc able to optimize it
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* as well as possible and (b) trying to avoid writing the same thing
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* over and over again with slight variations and possibly making a
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* mistake somewhere.
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*/
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/*
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* Thanks to James van Artsdalen for a better timing-fix than
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* the two short jumps: using outb's to a nonexistent port seems
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* to guarantee better timings even on fast machines.
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*
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* On the other hand, I'd like to be sure of a non-existent port:
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* I feel a bit unsafe about using 0x80 (should be safe, though)
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*
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* Linus
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*/
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/*
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* Bit simplified and optimized by Jan Hubicka
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* Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999.
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*
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* isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added,
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* isa_read[wl] and isa_write[wl] fixed
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* - Arnaldo Carvalho de Melo <acme@conectiva.com.br>
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*/
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#define ARCH_HAS_IOREMAP_WC
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#define ARCH_HAS_IOREMAP_WT
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#include <linux/string.h>
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#include <linux/compiler.h>
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#include <asm/page.h>
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#include <asm/early_ioremap.h>
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#include <asm/pgtable_types.h>
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#define build_mmio_read(name, size, type, reg, barrier) \
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static inline type name(const volatile void __iomem *addr) \
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{ type ret; asm volatile("mov" size " %1,%0":reg (ret) \
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:"m" (*(volatile type __force *)addr) barrier); return ret; }
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#define build_mmio_write(name, size, type, reg, barrier) \
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static inline void name(type val, volatile void __iomem *addr) \
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{ asm volatile("mov" size " %0,%1": :reg (val), \
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"m" (*(volatile type __force *)addr) barrier); }
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build_mmio_read(readb, "b", unsigned char, "=q", :"memory")
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build_mmio_read(readw, "w", unsigned short, "=r", :"memory")
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build_mmio_read(readl, "l", unsigned int, "=r", :"memory")
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build_mmio_read(__readb, "b", unsigned char, "=q", )
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build_mmio_read(__readw, "w", unsigned short, "=r", )
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build_mmio_read(__readl, "l", unsigned int, "=r", )
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build_mmio_write(writeb, "b", unsigned char, "q", :"memory")
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build_mmio_write(writew, "w", unsigned short, "r", :"memory")
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build_mmio_write(writel, "l", unsigned int, "r", :"memory")
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build_mmio_write(__writeb, "b", unsigned char, "q", )
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build_mmio_write(__writew, "w", unsigned short, "r", )
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build_mmio_write(__writel, "l", unsigned int, "r", )
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#define readb readb
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#define readw readw
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#define readl readl
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#define readb_relaxed(a) __readb(a)
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#define readw_relaxed(a) __readw(a)
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#define readl_relaxed(a) __readl(a)
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#define __raw_readb __readb
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#define __raw_readw __readw
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#define __raw_readl __readl
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#define writeb writeb
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#define writew writew
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#define writel writel
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#define writeb_relaxed(v, a) __writeb(v, a)
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#define writew_relaxed(v, a) __writew(v, a)
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#define writel_relaxed(v, a) __writel(v, a)
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#define __raw_writeb __writeb
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#define __raw_writew __writew
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#define __raw_writel __writel
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#define mmiowb() barrier()
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#ifdef CONFIG_X86_64
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build_mmio_read(readq, "q", u64, "=r", :"memory")
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build_mmio_read(__readq, "q", u64, "=r", )
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build_mmio_write(writeq, "q", u64, "r", :"memory")
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build_mmio_write(__writeq, "q", u64, "r", )
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#define readq_relaxed(a) __readq(a)
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#define writeq_relaxed(v, a) __writeq(v, a)
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#define __raw_readq __readq
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#define __raw_writeq __writeq
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/* Let people know that we have them */
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#define readq readq
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#define writeq writeq
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#endif
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#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
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extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
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extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
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/**
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* virt_to_phys - map virtual addresses to physical
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* @address: address to remap
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*
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* The returned physical address is the physical (CPU) mapping for
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* the memory address given. It is only valid to use this function on
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* addresses directly mapped or allocated via kmalloc.
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*
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* This function does not give bus mappings for DMA transfers. In
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* almost all conceivable cases a device driver should not be using
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* this function
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*/
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static inline phys_addr_t virt_to_phys(volatile void *address)
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{
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return __pa(address);
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}
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#define virt_to_phys virt_to_phys
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/**
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* phys_to_virt - map physical address to virtual
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* @address: address to remap
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*
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* The returned virtual address is a current CPU mapping for
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* the memory address given. It is only valid to use this function on
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* addresses that have a kernel mapping
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*
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* This function does not handle bus mappings for DMA transfers. In
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* almost all conceivable cases a device driver should not be using
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* this function
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*/
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static inline void *phys_to_virt(phys_addr_t address)
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{
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return __va(address);
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}
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#define phys_to_virt phys_to_virt
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/*
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* Change "struct page" to physical address.
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*/
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#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
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/*
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* ISA I/O bus memory addresses are 1:1 with the physical address.
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* However, we truncate the address to unsigned int to avoid undesirable
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* promitions in legacy drivers.
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*/
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static inline unsigned int isa_virt_to_bus(volatile void *address)
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{
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return (unsigned int)virt_to_phys(address);
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}
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#define isa_page_to_bus(page) ((unsigned int)page_to_phys(page))
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#define isa_bus_to_virt phys_to_virt
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/*
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* However PCI ones are not necessarily 1:1 and therefore these interfaces
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* are forbidden in portable PCI drivers.
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*
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* Allow them on x86 for legacy drivers, though.
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*/
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#define virt_to_bus virt_to_phys
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#define bus_to_virt phys_to_virt
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/*
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* The default ioremap() behavior is non-cached; if you need something
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* else, you probably want one of the following.
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*/
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extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size);
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#define ioremap_nocache ioremap_nocache
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extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size);
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#define ioremap_uc ioremap_uc
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extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size);
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#define ioremap_cache ioremap_cache
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extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, unsigned long prot_val);
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#define ioremap_prot ioremap_prot
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/**
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* ioremap - map bus memory into CPU space
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* @offset: bus address of the memory
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* @size: size of the resource to map
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*
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* ioremap performs a platform specific sequence of operations to
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* make bus memory CPU accessible via the readb/readw/readl/writeb/
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* writew/writel functions and the other mmio helpers. The returned
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* address is not guaranteed to be usable directly as a virtual
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* address.
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*
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* If the area you are trying to map is a PCI BAR you should have a
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* look at pci_iomap().
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*/
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static inline void __iomem *ioremap(resource_size_t offset, unsigned long size)
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{
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return ioremap_nocache(offset, size);
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}
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#define ioremap ioremap
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extern void iounmap(volatile void __iomem *addr);
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#define iounmap iounmap
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extern void set_iounmap_nonlazy(void);
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#ifdef __KERNEL__
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#include <asm-generic/iomap.h>
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/*
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* ISA space is 'always mapped' on a typical x86 system, no need to
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* explicitly ioremap() it. The fact that the ISA IO space is mapped
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* to PAGE_OFFSET is pure coincidence - it does not mean ISA values
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* are physical addresses. The following constant pointer can be
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* used as the IO-area pointer (it can be iounmapped as well, so the
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* analogy with PCI is quite large):
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*/
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#define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET))
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#endif /* __KERNEL__ */
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extern void native_io_delay(void);
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extern int io_delay_type;
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extern void io_delay_init(void);
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#if defined(CONFIG_PARAVIRT)
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#include <asm/paravirt.h>
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#else
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static inline void slow_down_io(void)
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{
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native_io_delay();
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#ifdef REALLY_SLOW_IO
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native_io_delay();
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native_io_delay();
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native_io_delay();
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#endif
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}
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#endif
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#ifdef CONFIG_AMD_MEM_ENCRYPT
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#include <linux/jump_label.h>
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extern struct static_key_false sev_enable_key;
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static inline bool sev_key_active(void)
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{
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return static_branch_unlikely(&sev_enable_key);
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}
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#else /* !CONFIG_AMD_MEM_ENCRYPT */
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static inline bool sev_key_active(void) { return false; }
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#endif /* CONFIG_AMD_MEM_ENCRYPT */
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#define BUILDIO(bwl, bw, type) \
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static inline void out##bwl(unsigned type value, int port) \
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{ \
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asm volatile("out" #bwl " %" #bw "0, %w1" \
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: : "a"(value), "Nd"(port)); \
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} \
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\
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static inline unsigned type in##bwl(int port) \
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{ \
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unsigned type value; \
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asm volatile("in" #bwl " %w1, %" #bw "0" \
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: "=a"(value) : "Nd"(port)); \
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return value; \
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} \
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\
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static inline void out##bwl##_p(unsigned type value, int port) \
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{ \
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out##bwl(value, port); \
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slow_down_io(); \
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} \
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\
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static inline unsigned type in##bwl##_p(int port) \
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{ \
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unsigned type value = in##bwl(port); \
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slow_down_io(); \
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return value; \
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} \
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\
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static inline void outs##bwl(int port, const void *addr, unsigned long count) \
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{ \
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if (sev_key_active()) { \
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unsigned type *value = (unsigned type *)addr; \
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while (count) { \
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out##bwl(*value, port); \
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value++; \
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count--; \
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} \
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} else { \
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asm volatile("rep; outs" #bwl \
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: "+S"(addr), "+c"(count) \
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: "d"(port) : "memory"); \
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} \
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} \
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\
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static inline void ins##bwl(int port, void *addr, unsigned long count) \
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{ \
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if (sev_key_active()) { \
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unsigned type *value = (unsigned type *)addr; \
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while (count) { \
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*value = in##bwl(port); \
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value++; \
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count--; \
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} \
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} else { \
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asm volatile("rep; ins" #bwl \
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: "+D"(addr), "+c"(count) \
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: "d"(port) : "memory"); \
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} \
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}
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BUILDIO(b, b, char)
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BUILDIO(w, w, short)
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BUILDIO(l, , int)
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#define inb inb
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#define inw inw
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#define inl inl
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#define inb_p inb_p
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#define inw_p inw_p
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#define inl_p inl_p
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#define insb insb
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#define insw insw
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#define insl insl
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#define outb outb
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#define outw outw
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#define outl outl
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#define outb_p outb_p
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#define outw_p outw_p
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#define outl_p outl_p
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#define outsb outsb
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#define outsw outsw
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#define outsl outsl
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extern void *xlate_dev_mem_ptr(phys_addr_t phys);
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extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr);
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#define xlate_dev_mem_ptr xlate_dev_mem_ptr
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#define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
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extern int ioremap_change_attr(unsigned long vaddr, unsigned long size,
|
||
|
|
enum page_cache_mode pcm);
|
||
|
|
extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size);
|
||
|
|
#define ioremap_wc ioremap_wc
|
||
|
|
extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size);
|
||
|
|
#define ioremap_wt ioremap_wt
|
||
|
|
|
||
|
|
extern bool is_early_ioremap_ptep(pte_t *ptep);
|
||
|
|
|
||
|
|
#ifdef CONFIG_XEN
|
||
|
|
#include <xen/xen.h>
|
||
|
|
struct bio_vec;
|
||
|
|
|
||
|
|
extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1,
|
||
|
|
const struct bio_vec *vec2);
|
||
|
|
|
||
|
|
#define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \
|
||
|
|
(__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \
|
||
|
|
(!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2)))
|
||
|
|
#endif /* CONFIG_XEN */
|
||
|
|
|
||
|
|
#define IO_SPACE_LIMIT 0xffff
|
||
|
|
|
||
|
|
#include <asm-generic/io.h>
|
||
|
|
#undef PCI_IOBASE
|
||
|
|
|
||
|
|
#ifdef CONFIG_MTRR
|
||
|
|
extern int __must_check arch_phys_wc_index(int handle);
|
||
|
|
#define arch_phys_wc_index arch_phys_wc_index
|
||
|
|
|
||
|
|
extern int __must_check arch_phys_wc_add(unsigned long base,
|
||
|
|
unsigned long size);
|
||
|
|
extern void arch_phys_wc_del(int handle);
|
||
|
|
#define arch_phys_wc_add arch_phys_wc_add
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifdef CONFIG_X86_PAT
|
||
|
|
extern int arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size);
|
||
|
|
extern void arch_io_free_memtype_wc(resource_size_t start, resource_size_t size);
|
||
|
|
#define arch_io_reserve_memtype_wc arch_io_reserve_memtype_wc
|
||
|
|
#endif
|
||
|
|
|
||
|
|
extern bool arch_memremap_can_ram_remap(resource_size_t offset,
|
||
|
|
unsigned long size,
|
||
|
|
unsigned long flags);
|
||
|
|
#define arch_memremap_can_ram_remap arch_memremap_can_ram_remap
|
||
|
|
|
||
|
|
extern bool phys_mem_access_encrypted(unsigned long phys_addr,
|
||
|
|
unsigned long size);
|
||
|
|
|
||
|
|
#endif /* _ASM_X86_IO_H */
|