391 lines
13 KiB
C
391 lines
13 KiB
C
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/******************************************************************************
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* arch-x86_32.h
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*
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* Guest OS interface to x86 Xen.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to
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* deal in the Software without restriction, including without limitation the
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* rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Copyright (c) 2004-2006, K A Fraser
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*/
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#ifndef _ASM_X86_XEN_INTERFACE_H
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#define _ASM_X86_XEN_INTERFACE_H
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/*
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* XEN_GUEST_HANDLE represents a guest pointer, when passed as a field
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* in a struct in memory.
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* XEN_GUEST_HANDLE_PARAM represent a guest pointer, when passed as an
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* hypercall argument.
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* XEN_GUEST_HANDLE_PARAM and XEN_GUEST_HANDLE are the same on X86 but
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* they might not be on other architectures.
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*/
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#ifdef __XEN__
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#define __DEFINE_GUEST_HANDLE(name, type) \
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typedef struct { type *p; } __guest_handle_ ## name
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#else
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#define __DEFINE_GUEST_HANDLE(name, type) \
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typedef type * __guest_handle_ ## name
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#endif
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#define DEFINE_GUEST_HANDLE_STRUCT(name) \
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__DEFINE_GUEST_HANDLE(name, struct name)
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#define DEFINE_GUEST_HANDLE(name) __DEFINE_GUEST_HANDLE(name, name)
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#define GUEST_HANDLE(name) __guest_handle_ ## name
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#ifdef __XEN__
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#if defined(__i386__)
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#define set_xen_guest_handle(hnd, val) \
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do { \
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if (sizeof(hnd) == 8) \
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*(uint64_t *)&(hnd) = 0; \
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(hnd).p = val; \
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} while (0)
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#elif defined(__x86_64__)
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#define set_xen_guest_handle(hnd, val) do { (hnd).p = val; } while (0)
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#endif
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#else
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#if defined(__i386__)
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#define set_xen_guest_handle(hnd, val) \
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do { \
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if (sizeof(hnd) == 8) \
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*(uint64_t *)&(hnd) = 0; \
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(hnd) = val; \
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} while (0)
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#elif defined(__x86_64__)
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#define set_xen_guest_handle(hnd, val) do { (hnd) = val; } while (0)
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#endif
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#endif
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#ifndef __ASSEMBLY__
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/* Explicitly size integers that represent pfns in the public interface
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* with Xen so that on ARM we can have one ABI that works for 32 and 64
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* bit guests. */
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typedef unsigned long xen_pfn_t;
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#define PRI_xen_pfn "lx"
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typedef unsigned long xen_ulong_t;
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#define PRI_xen_ulong "lx"
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typedef long xen_long_t;
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#define PRI_xen_long "lx"
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/* Guest handles for primitive C types. */
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__DEFINE_GUEST_HANDLE(uchar, unsigned char);
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__DEFINE_GUEST_HANDLE(uint, unsigned int);
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DEFINE_GUEST_HANDLE(char);
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DEFINE_GUEST_HANDLE(int);
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DEFINE_GUEST_HANDLE(void);
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DEFINE_GUEST_HANDLE(uint64_t);
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DEFINE_GUEST_HANDLE(uint32_t);
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DEFINE_GUEST_HANDLE(xen_pfn_t);
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DEFINE_GUEST_HANDLE(xen_ulong_t);
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#endif
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#ifndef HYPERVISOR_VIRT_START
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#define HYPERVISOR_VIRT_START mk_unsigned_long(__HYPERVISOR_VIRT_START)
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#endif
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#define MACH2PHYS_VIRT_START mk_unsigned_long(__MACH2PHYS_VIRT_START)
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#define MACH2PHYS_VIRT_END mk_unsigned_long(__MACH2PHYS_VIRT_END)
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#define MACH2PHYS_NR_ENTRIES ((MACH2PHYS_VIRT_END-MACH2PHYS_VIRT_START)>>__MACH2PHYS_SHIFT)
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/* Maximum number of virtual CPUs in multi-processor guests. */
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#define MAX_VIRT_CPUS 32
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/*
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* SEGMENT DESCRIPTOR TABLES
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*/
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/*
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* A number of GDT entries are reserved by Xen. These are not situated at the
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* start of the GDT because some stupid OSes export hard-coded selector values
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* in their ABI. These hard-coded values are always near the start of the GDT,
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* so Xen places itself out of the way, at the far end of the GDT.
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*
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* NB The LDT is set using the MMUEXT_SET_LDT op of HYPERVISOR_mmuext_op
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*/
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#define FIRST_RESERVED_GDT_PAGE 14
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#define FIRST_RESERVED_GDT_BYTE (FIRST_RESERVED_GDT_PAGE * 4096)
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#define FIRST_RESERVED_GDT_ENTRY (FIRST_RESERVED_GDT_BYTE / 8)
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/*
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* Send an array of these to HYPERVISOR_set_trap_table().
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* Terminate the array with a sentinel entry, with traps[].address==0.
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* The privilege level specifies which modes may enter a trap via a software
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* interrupt. On x86/64, since rings 1 and 2 are unavailable, we allocate
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* privilege levels as follows:
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* Level == 0: No one may enter
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* Level == 1: Kernel may enter
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* Level == 2: Kernel may enter
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* Level == 3: Everyone may enter
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*/
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#define TI_GET_DPL(_ti) ((_ti)->flags & 3)
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#define TI_GET_IF(_ti) ((_ti)->flags & 4)
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#define TI_SET_DPL(_ti, _dpl) ((_ti)->flags |= (_dpl))
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#define TI_SET_IF(_ti, _if) ((_ti)->flags |= ((!!(_if))<<2))
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#ifndef __ASSEMBLY__
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struct trap_info {
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uint8_t vector; /* exception vector */
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uint8_t flags; /* 0-3: privilege level; 4: clear event enable? */
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uint16_t cs; /* code selector */
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unsigned long address; /* code offset */
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};
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DEFINE_GUEST_HANDLE_STRUCT(trap_info);
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struct arch_shared_info {
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/*
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* Number of valid entries in the p2m table(s) anchored at
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* pfn_to_mfn_frame_list_list and/or p2m_vaddr.
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*/
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unsigned long max_pfn;
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/*
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* Frame containing list of mfns containing list of mfns containing p2m.
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* A value of 0 indicates it has not yet been set up, ~0 indicates it
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* has been set to invalid e.g. due to the p2m being too large for the
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* 3-level p2m tree. In this case the linear mapper p2m list anchored
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* at p2m_vaddr is to be used.
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*/
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xen_pfn_t pfn_to_mfn_frame_list_list;
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unsigned long nmi_reason;
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/*
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* Following three fields are valid if p2m_cr3 contains a value
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* different from 0.
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* p2m_cr3 is the root of the address space where p2m_vaddr is valid.
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* p2m_cr3 is in the same format as a cr3 value in the vcpu register
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* state and holds the folded machine frame number (via xen_pfn_to_cr3)
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* of a L3 or L4 page table.
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* p2m_vaddr holds the virtual address of the linear p2m list. All
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* entries in the range [0...max_pfn[ are accessible via this pointer.
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* p2m_generation will be incremented by the guest before and after each
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* change of the mappings of the p2m list. p2m_generation starts at 0
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* and a value with the least significant bit set indicates that a
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* mapping update is in progress. This allows guest external software
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* (e.g. in Dom0) to verify that read mappings are consistent and
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* whether they have changed since the last check.
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* Modifying a p2m element in the linear p2m list is allowed via an
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* atomic write only.
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*/
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unsigned long p2m_cr3; /* cr3 value of the p2m address space */
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unsigned long p2m_vaddr; /* virtual address of the p2m list */
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unsigned long p2m_generation; /* generation count of p2m mapping */
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};
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#endif /* !__ASSEMBLY__ */
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#ifdef CONFIG_X86_32
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#include <asm/xen/interface_32.h>
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#else
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#include <asm/xen/interface_64.h>
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#endif
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#include <asm/pvclock-abi.h>
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#ifndef __ASSEMBLY__
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/*
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* The following is all CPU context. Note that the fpu_ctxt block is filled
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* in by FXSAVE if the CPU has feature FXSR; otherwise FSAVE is used.
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*
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* Also note that when calling DOMCTL_setvcpucontext and VCPU_initialise
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* for HVM and PVH guests, not all information in this structure is updated:
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*
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* - For HVM guests, the structures read include: fpu_ctxt (if
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* VGCT_I387_VALID is set), flags, user_regs, debugreg[*]
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*
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* - PVH guests are the same as HVM guests, but additionally use ctrlreg[3] to
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* set cr3. All other fields not used should be set to 0.
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*/
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struct vcpu_guest_context {
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/* FPU registers come first so they can be aligned for FXSAVE/FXRSTOR. */
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struct { char x[512]; } fpu_ctxt; /* User-level FPU registers */
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#define VGCF_I387_VALID (1<<0)
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#define VGCF_IN_KERNEL (1<<2)
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#define _VGCF_i387_valid 0
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#define VGCF_i387_valid (1<<_VGCF_i387_valid)
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#define _VGCF_in_kernel 2
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#define VGCF_in_kernel (1<<_VGCF_in_kernel)
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#define _VGCF_failsafe_disables_events 3
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#define VGCF_failsafe_disables_events (1<<_VGCF_failsafe_disables_events)
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#define _VGCF_syscall_disables_events 4
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#define VGCF_syscall_disables_events (1<<_VGCF_syscall_disables_events)
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#define _VGCF_online 5
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#define VGCF_online (1<<_VGCF_online)
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unsigned long flags; /* VGCF_* flags */
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struct cpu_user_regs user_regs; /* User-level CPU registers */
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struct trap_info trap_ctxt[256]; /* Virtual IDT */
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unsigned long ldt_base, ldt_ents; /* LDT (linear address, # ents) */
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unsigned long gdt_frames[16], gdt_ents; /* GDT (machine frames, # ents) */
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unsigned long kernel_ss, kernel_sp; /* Virtual TSS (only SS1/SP1) */
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/* NB. User pagetable on x86/64 is placed in ctrlreg[1]. */
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unsigned long ctrlreg[8]; /* CR0-CR7 (control registers) */
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unsigned long debugreg[8]; /* DB0-DB7 (debug registers) */
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#ifdef __i386__
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unsigned long event_callback_cs; /* CS:EIP of event callback */
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unsigned long event_callback_eip;
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unsigned long failsafe_callback_cs; /* CS:EIP of failsafe callback */
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unsigned long failsafe_callback_eip;
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#else
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unsigned long event_callback_eip;
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unsigned long failsafe_callback_eip;
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unsigned long syscall_callback_eip;
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#endif
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unsigned long vm_assist; /* VMASST_TYPE_* bitmap */
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#ifdef __x86_64__
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/* Segment base addresses. */
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uint64_t fs_base;
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uint64_t gs_base_kernel;
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uint64_t gs_base_user;
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#endif
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};
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DEFINE_GUEST_HANDLE_STRUCT(vcpu_guest_context);
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/* AMD PMU registers and structures */
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struct xen_pmu_amd_ctxt {
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/*
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* Offsets to counter and control MSRs (relative to xen_pmu_arch.c.amd).
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* For PV(H) guests these fields are RO.
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*/
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uint32_t counters;
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uint32_t ctrls;
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/* Counter MSRs */
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#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
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uint64_t regs[];
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#elif defined(__GNUC__)
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uint64_t regs[0];
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#endif
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};
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/* Intel PMU registers and structures */
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struct xen_pmu_cntr_pair {
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uint64_t counter;
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uint64_t control;
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};
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struct xen_pmu_intel_ctxt {
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/*
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* Offsets to fixed and architectural counter MSRs (relative to
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* xen_pmu_arch.c.intel).
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* For PV(H) guests these fields are RO.
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*/
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uint32_t fixed_counters;
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uint32_t arch_counters;
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/* PMU registers */
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uint64_t global_ctrl;
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uint64_t global_ovf_ctrl;
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uint64_t global_status;
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uint64_t fixed_ctrl;
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uint64_t ds_area;
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uint64_t pebs_enable;
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uint64_t debugctl;
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/* Fixed and architectural counter MSRs */
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#if defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L
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uint64_t regs[];
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#elif defined(__GNUC__)
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uint64_t regs[0];
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#endif
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};
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/* Sampled domain's registers */
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struct xen_pmu_regs {
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uint64_t ip;
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uint64_t sp;
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uint64_t flags;
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uint16_t cs;
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uint16_t ss;
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uint8_t cpl;
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uint8_t pad[3];
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};
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/* PMU flags */
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#define PMU_CACHED (1<<0) /* PMU MSRs are cached in the context */
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#define PMU_SAMPLE_USER (1<<1) /* Sample is from user or kernel mode */
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#define PMU_SAMPLE_REAL (1<<2) /* Sample is from realmode */
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#define PMU_SAMPLE_PV (1<<3) /* Sample from a PV guest */
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/*
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* Architecture-specific information describing state of the processor at
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* the time of PMU interrupt.
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* Fields of this structure marked as RW for guest should only be written by
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* the guest when PMU_CACHED bit in pmu_flags is set (which is done by the
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* hypervisor during PMU interrupt). Hypervisor will read updated data in
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* XENPMU_flush hypercall and clear PMU_CACHED bit.
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*/
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struct xen_pmu_arch {
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union {
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/*
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* Processor's registers at the time of interrupt.
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* WO for hypervisor, RO for guests.
|
||
|
|
*/
|
||
|
|
struct xen_pmu_regs regs;
|
||
|
|
/*
|
||
|
|
* Padding for adding new registers to xen_pmu_regs in
|
||
|
|
* the future
|
||
|
|
*/
|
||
|
|
#define XENPMU_REGS_PAD_SZ 64
|
||
|
|
uint8_t pad[XENPMU_REGS_PAD_SZ];
|
||
|
|
} r;
|
||
|
|
|
||
|
|
/* WO for hypervisor, RO for guest */
|
||
|
|
uint64_t pmu_flags;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* APIC LVTPC register.
|
||
|
|
* RW for both hypervisor and guest.
|
||
|
|
* Only APIC_LVT_MASKED bit is loaded by the hypervisor into hardware
|
||
|
|
* during XENPMU_flush or XENPMU_lvtpc_set.
|
||
|
|
*/
|
||
|
|
union {
|
||
|
|
uint32_t lapic_lvtpc;
|
||
|
|
uint64_t pad;
|
||
|
|
} l;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Vendor-specific PMU registers.
|
||
|
|
* RW for both hypervisor and guest (see exceptions above).
|
||
|
|
* Guest's updates to this field are verified and then loaded by the
|
||
|
|
* hypervisor into hardware during XENPMU_flush
|
||
|
|
*/
|
||
|
|
union {
|
||
|
|
struct xen_pmu_amd_ctxt amd;
|
||
|
|
struct xen_pmu_intel_ctxt intel;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Padding for contexts (fixed parts only, does not include
|
||
|
|
* MSR banks that are specified by offsets)
|
||
|
|
*/
|
||
|
|
#define XENPMU_CTXT_PAD_SZ 128
|
||
|
|
uint8_t pad[XENPMU_CTXT_PAD_SZ];
|
||
|
|
} c;
|
||
|
|
};
|
||
|
|
|
||
|
|
#endif /* !__ASSEMBLY__ */
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Prefix forces emulation of some non-trapping instructions.
|
||
|
|
* Currently only CPUID.
|
||
|
|
*/
|
||
|
|
#ifdef __ASSEMBLY__
|
||
|
|
#define XEN_EMULATE_PREFIX .byte 0x0f,0x0b,0x78,0x65,0x6e ;
|
||
|
|
#define XEN_CPUID XEN_EMULATE_PREFIX cpuid
|
||
|
|
#else
|
||
|
|
#define XEN_EMULATE_PREFIX ".byte 0x0f,0x0b,0x78,0x65,0x6e ; "
|
||
|
|
#define XEN_CPUID XEN_EMULATE_PREFIX "cpuid"
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif /* _ASM_X86_XEN_INTERFACE_H */
|