492 lines
12 KiB
C
492 lines
12 KiB
C
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/*
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* Copyright © 2016 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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*/
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#include "intel_uc.h"
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#include "intel_guc_submission.h"
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#include "intel_guc.h"
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#include "i915_drv.h"
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static void guc_free_load_err_log(struct intel_guc *guc);
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/* Reset GuC providing us with fresh state for both GuC and HuC.
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*/
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static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
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{
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int ret;
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u32 guc_status;
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ret = intel_reset_guc(dev_priv);
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if (ret) {
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DRM_ERROR("Failed to reset GuC, ret = %d\n", ret);
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return ret;
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}
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guc_status = I915_READ(GUC_STATUS);
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WARN(!(guc_status & GS_MIA_IN_RESET),
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"GuC status: 0x%x, MIA core expected to be in reset\n",
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guc_status);
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return ret;
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}
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static int __get_platform_enable_guc(struct drm_i915_private *i915)
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{
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struct intel_uc_fw *guc_fw = &i915->guc.fw;
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struct intel_uc_fw *huc_fw = &i915->huc.fw;
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int enable_guc = 0;
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/* Default is to enable GuC/HuC if we know their firmwares */
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if (intel_uc_fw_is_selected(guc_fw))
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enable_guc |= ENABLE_GUC_SUBMISSION;
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if (intel_uc_fw_is_selected(huc_fw))
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enable_guc |= ENABLE_GUC_LOAD_HUC;
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/* Any platform specific fine-tuning can be done here */
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return enable_guc;
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}
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static int __get_default_guc_log_level(struct drm_i915_private *i915)
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{
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int guc_log_level;
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if (!HAS_GUC(i915) || !intel_uc_is_using_guc())
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guc_log_level = GUC_LOG_LEVEL_DISABLED;
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else if (IS_ENABLED(CONFIG_DRM_I915_DEBUG) ||
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IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
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guc_log_level = GUC_LOG_LEVEL_MAX;
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else
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guc_log_level = GUC_LOG_LEVEL_NON_VERBOSE;
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/* Any platform specific fine-tuning can be done here */
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return guc_log_level;
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}
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/**
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* sanitize_options_early - sanitize uC related modparam options
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* @i915: device private
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*
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* In case of "enable_guc" option this function will attempt to modify
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* it only if it was initially set to "auto(-1)". Default value for this
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* modparam varies between platforms and it is hardcoded in driver code.
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* Any other modparam value is only monitored against availability of the
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* related hardware or firmware definitions.
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*
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* In case of "guc_log_level" option this function will attempt to modify
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* it only if it was initially set to "auto(-1)" or if initial value was
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* "enable(1..4)" on platforms without the GuC. Default value for this
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* modparam varies between platforms and is usually set to "disable(0)"
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* unless GuC is enabled on given platform and the driver is compiled with
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* debug config when this modparam will default to "enable(1..4)".
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*/
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static void sanitize_options_early(struct drm_i915_private *i915)
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{
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struct intel_uc_fw *guc_fw = &i915->guc.fw;
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struct intel_uc_fw *huc_fw = &i915->huc.fw;
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/* A negative value means "use platform default" */
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if (i915_modparams.enable_guc < 0)
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i915_modparams.enable_guc = __get_platform_enable_guc(i915);
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DRM_DEBUG_DRIVER("enable_guc=%d (submission:%s huc:%s)\n",
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i915_modparams.enable_guc,
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yesno(intel_uc_is_using_guc_submission()),
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yesno(intel_uc_is_using_huc()));
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/* Verify GuC firmware availability */
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if (intel_uc_is_using_guc() && !intel_uc_fw_is_selected(guc_fw)) {
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DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
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"enable_guc", i915_modparams.enable_guc,
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!HAS_GUC(i915) ? "no GuC hardware" :
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"no GuC firmware");
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}
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/* Verify HuC firmware availability */
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if (intel_uc_is_using_huc() && !intel_uc_fw_is_selected(huc_fw)) {
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DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
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"enable_guc", i915_modparams.enable_guc,
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!HAS_HUC(i915) ? "no HuC hardware" :
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"no HuC firmware");
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}
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/* A negative value means "use platform/config default" */
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if (i915_modparams.guc_log_level < 0)
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i915_modparams.guc_log_level =
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__get_default_guc_log_level(i915);
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if (i915_modparams.guc_log_level > 0 && !intel_uc_is_using_guc()) {
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DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
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"guc_log_level", i915_modparams.guc_log_level,
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!HAS_GUC(i915) ? "no GuC hardware" :
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"GuC not enabled");
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i915_modparams.guc_log_level = 0;
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}
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if (i915_modparams.guc_log_level > GUC_LOG_LEVEL_MAX) {
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DRM_WARN("Incompatible option detected: %s=%d, %s!\n",
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"guc_log_level", i915_modparams.guc_log_level,
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"verbosity too high");
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i915_modparams.guc_log_level = GUC_LOG_LEVEL_MAX;
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}
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DRM_DEBUG_DRIVER("guc_log_level=%d (enabled:%s, verbose:%s, verbosity:%d)\n",
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i915_modparams.guc_log_level,
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yesno(i915_modparams.guc_log_level),
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yesno(GUC_LOG_LEVEL_IS_VERBOSE(i915_modparams.guc_log_level)),
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GUC_LOG_LEVEL_TO_VERBOSITY(i915_modparams.guc_log_level));
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/* Make sure that sanitization was done */
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GEM_BUG_ON(i915_modparams.enable_guc < 0);
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GEM_BUG_ON(i915_modparams.guc_log_level < 0);
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}
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void intel_uc_init_early(struct drm_i915_private *i915)
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{
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struct intel_guc *guc = &i915->guc;
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struct intel_huc *huc = &i915->huc;
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intel_guc_init_early(guc);
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intel_huc_init_early(huc);
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sanitize_options_early(i915);
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}
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void intel_uc_cleanup_early(struct drm_i915_private *i915)
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{
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struct intel_guc *guc = &i915->guc;
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guc_free_load_err_log(guc);
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}
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/**
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* intel_uc_init_mmio - setup uC MMIO access
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* @i915: device private
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*
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* Setup minimal state necessary for MMIO accesses later in the
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* initialization sequence.
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*/
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void intel_uc_init_mmio(struct drm_i915_private *i915)
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{
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intel_guc_init_send_regs(&i915->guc);
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}
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static void guc_capture_load_err_log(struct intel_guc *guc)
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{
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if (!guc->log.vma || !intel_guc_log_get_level(&guc->log))
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return;
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if (!guc->load_err_log)
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guc->load_err_log = i915_gem_object_get(guc->log.vma->obj);
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return;
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}
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static void guc_free_load_err_log(struct intel_guc *guc)
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{
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if (guc->load_err_log)
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i915_gem_object_put(guc->load_err_log);
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}
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static int guc_enable_communication(struct intel_guc *guc)
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{
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struct drm_i915_private *i915 = guc_to_i915(guc);
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gen9_enable_guc_interrupts(i915);
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if (HAS_GUC_CT(i915))
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return intel_guc_ct_enable(&guc->ct);
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guc->send = intel_guc_send_mmio;
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guc->handler = intel_guc_to_host_event_handler_mmio;
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return 0;
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}
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static void guc_disable_communication(struct intel_guc *guc)
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{
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struct drm_i915_private *i915 = guc_to_i915(guc);
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if (HAS_GUC_CT(i915))
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intel_guc_ct_disable(&guc->ct);
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gen9_disable_guc_interrupts(i915);
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guc->send = intel_guc_send_nop;
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guc->handler = intel_guc_to_host_event_handler_nop;
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}
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int intel_uc_init_misc(struct drm_i915_private *i915)
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{
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struct intel_guc *guc = &i915->guc;
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struct intel_huc *huc = &i915->huc;
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int ret;
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if (!USES_GUC(i915))
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return 0;
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ret = intel_guc_init_misc(guc);
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if (ret)
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return ret;
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if (USES_HUC(i915)) {
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ret = intel_huc_init_misc(huc);
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if (ret)
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goto err_guc;
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}
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return 0;
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err_guc:
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intel_guc_fini_misc(guc);
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return ret;
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}
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void intel_uc_fini_misc(struct drm_i915_private *i915)
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{
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struct intel_guc *guc = &i915->guc;
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struct intel_huc *huc = &i915->huc;
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if (!USES_GUC(i915))
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return;
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if (USES_HUC(i915))
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intel_huc_fini_misc(huc);
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intel_guc_fini_misc(guc);
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}
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int intel_uc_init(struct drm_i915_private *i915)
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{
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struct intel_guc *guc = &i915->guc;
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int ret;
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if (!USES_GUC(i915))
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return 0;
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if (!HAS_GUC(i915))
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return -ENODEV;
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ret = intel_guc_init(guc);
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if (ret)
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return ret;
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if (USES_GUC_SUBMISSION(i915)) {
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/*
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* This is stuff we need to have available at fw load time
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* if we are planning to enable submission later
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*/
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ret = intel_guc_submission_init(guc);
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if (ret) {
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intel_guc_fini(guc);
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return ret;
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}
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}
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return 0;
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}
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void intel_uc_fini(struct drm_i915_private *i915)
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{
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struct intel_guc *guc = &i915->guc;
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if (!USES_GUC(i915))
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return;
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GEM_BUG_ON(!HAS_GUC(i915));
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if (USES_GUC_SUBMISSION(i915))
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intel_guc_submission_fini(guc);
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intel_guc_fini(guc);
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}
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void intel_uc_sanitize(struct drm_i915_private *i915)
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{
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struct intel_guc *guc = &i915->guc;
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struct intel_huc *huc = &i915->huc;
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if (!USES_GUC(i915))
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return;
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GEM_BUG_ON(!HAS_GUC(i915));
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guc_disable_communication(guc);
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intel_huc_sanitize(huc);
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intel_guc_sanitize(guc);
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__intel_uc_reset_hw(i915);
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}
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int intel_uc_init_hw(struct drm_i915_private *i915)
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{
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struct intel_guc *guc = &i915->guc;
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struct intel_huc *huc = &i915->huc;
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int ret, attempts;
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if (!USES_GUC(i915))
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return 0;
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GEM_BUG_ON(!HAS_GUC(i915));
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gen9_reset_guc_interrupts(i915);
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/* WaEnableuKernelHeaderValidFix:skl */
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/* WaEnableGuCBootHashCheckNotSet:skl,bxt,kbl */
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if (IS_GEN9(i915))
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attempts = 3;
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else
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attempts = 1;
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|
while (attempts--) {
|
||
|
|
/*
|
||
|
|
* Always reset the GuC just before (re)loading, so
|
||
|
|
* that the state and timing are fairly predictable
|
||
|
|
*/
|
||
|
|
ret = __intel_uc_reset_hw(i915);
|
||
|
|
if (ret)
|
||
|
|
goto err_out;
|
||
|
|
|
||
|
|
if (USES_HUC(i915)) {
|
||
|
|
ret = intel_huc_fw_upload(huc);
|
||
|
|
if (ret)
|
||
|
|
goto err_out;
|
||
|
|
}
|
||
|
|
|
||
|
|
intel_guc_init_params(guc);
|
||
|
|
ret = intel_guc_fw_upload(guc);
|
||
|
|
if (ret == 0 || ret != -EAGAIN)
|
||
|
|
break;
|
||
|
|
|
||
|
|
DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
|
||
|
|
"retry %d more time(s)\n", ret, attempts);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Did we succeded or run out of retries? */
|
||
|
|
if (ret)
|
||
|
|
goto err_log_capture;
|
||
|
|
|
||
|
|
ret = guc_enable_communication(guc);
|
||
|
|
if (ret)
|
||
|
|
goto err_log_capture;
|
||
|
|
|
||
|
|
if (USES_HUC(i915)) {
|
||
|
|
ret = intel_huc_auth(huc);
|
||
|
|
if (ret)
|
||
|
|
goto err_communication;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (USES_GUC_SUBMISSION(i915)) {
|
||
|
|
ret = intel_guc_submission_enable(guc);
|
||
|
|
if (ret)
|
||
|
|
goto err_communication;
|
||
|
|
}
|
||
|
|
|
||
|
|
dev_info(i915->drm.dev, "GuC firmware version %u.%u\n",
|
||
|
|
guc->fw.major_ver_found, guc->fw.minor_ver_found);
|
||
|
|
dev_info(i915->drm.dev, "GuC submission %s\n",
|
||
|
|
enableddisabled(USES_GUC_SUBMISSION(i915)));
|
||
|
|
dev_info(i915->drm.dev, "HuC %s\n",
|
||
|
|
enableddisabled(USES_HUC(i915)));
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
/*
|
||
|
|
* We've failed to load the firmware :(
|
||
|
|
*/
|
||
|
|
err_communication:
|
||
|
|
guc_disable_communication(guc);
|
||
|
|
err_log_capture:
|
||
|
|
guc_capture_load_err_log(guc);
|
||
|
|
err_out:
|
||
|
|
/*
|
||
|
|
* Note that there is no fallback as either user explicitly asked for
|
||
|
|
* the GuC or driver default option was to run with the GuC enabled.
|
||
|
|
*/
|
||
|
|
if (GEM_WARN_ON(ret == -EIO))
|
||
|
|
ret = -EINVAL;
|
||
|
|
|
||
|
|
dev_err(i915->drm.dev, "GuC initialization failed %d\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
void intel_uc_fini_hw(struct drm_i915_private *i915)
|
||
|
|
{
|
||
|
|
struct intel_guc *guc = &i915->guc;
|
||
|
|
|
||
|
|
if (!USES_GUC(i915))
|
||
|
|
return;
|
||
|
|
|
||
|
|
GEM_BUG_ON(!HAS_GUC(i915));
|
||
|
|
|
||
|
|
if (USES_GUC_SUBMISSION(i915))
|
||
|
|
intel_guc_submission_disable(guc);
|
||
|
|
|
||
|
|
guc_disable_communication(guc);
|
||
|
|
}
|
||
|
|
|
||
|
|
int intel_uc_suspend(struct drm_i915_private *i915)
|
||
|
|
{
|
||
|
|
struct intel_guc *guc = &i915->guc;
|
||
|
|
int err;
|
||
|
|
|
||
|
|
if (!USES_GUC(i915))
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
err = intel_guc_suspend(guc);
|
||
|
|
if (err) {
|
||
|
|
DRM_DEBUG_DRIVER("Failed to suspend GuC, err=%d", err);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
gen9_disable_guc_interrupts(i915);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int intel_uc_resume(struct drm_i915_private *i915)
|
||
|
|
{
|
||
|
|
struct intel_guc *guc = &i915->guc;
|
||
|
|
int err;
|
||
|
|
|
||
|
|
if (!USES_GUC(i915))
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
gen9_enable_guc_interrupts(i915);
|
||
|
|
|
||
|
|
err = intel_guc_resume(guc);
|
||
|
|
if (err) {
|
||
|
|
DRM_DEBUG_DRIVER("Failed to resume GuC, err=%d", err);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|