386 lines
9.3 KiB
C
386 lines
9.3 KiB
C
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/*
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* Copyright (C) 2013-2014 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "adreno_gpu.h"
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#define ANY_ID 0xff
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bool hang_debug = false;
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MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
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module_param_named(hang_debug, hang_debug, bool, 0600);
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static const struct adreno_info gpulist[] = {
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{
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.rev = ADRENO_REV(3, 0, 5, ANY_ID),
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.revn = 305,
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.name = "A305",
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.fw = {
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[ADRENO_FW_PM4] = "a300_pm4.fw",
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[ADRENO_FW_PFP] = "a300_pfp.fw",
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},
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.gmem = SZ_256K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a3xx_gpu_init,
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}, {
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.rev = ADRENO_REV(3, 0, 6, 0),
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.revn = 307, /* because a305c is revn==306 */
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.name = "A306",
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.fw = {
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[ADRENO_FW_PM4] = "a300_pm4.fw",
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[ADRENO_FW_PFP] = "a300_pfp.fw",
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},
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.gmem = SZ_128K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a3xx_gpu_init,
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}, {
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.rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID),
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.revn = 320,
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.name = "A320",
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.fw = {
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[ADRENO_FW_PM4] = "a300_pm4.fw",
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[ADRENO_FW_PFP] = "a300_pfp.fw",
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},
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.gmem = SZ_512K,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a3xx_gpu_init,
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}, {
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.rev = ADRENO_REV(3, 3, 0, ANY_ID),
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.revn = 330,
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.name = "A330",
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.fw = {
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[ADRENO_FW_PM4] = "a330_pm4.fw",
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[ADRENO_FW_PFP] = "a330_pfp.fw",
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},
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.gmem = SZ_1M,
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a3xx_gpu_init,
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}, {
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.rev = ADRENO_REV(4, 2, 0, ANY_ID),
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.revn = 420,
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.name = "A420",
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.fw = {
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[ADRENO_FW_PM4] = "a420_pm4.fw",
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[ADRENO_FW_PFP] = "a420_pfp.fw",
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},
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.gmem = (SZ_1M + SZ_512K),
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a4xx_gpu_init,
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}, {
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.rev = ADRENO_REV(4, 3, 0, ANY_ID),
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.revn = 430,
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.name = "A430",
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.fw = {
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[ADRENO_FW_PM4] = "a420_pm4.fw",
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[ADRENO_FW_PFP] = "a420_pfp.fw",
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},
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.gmem = (SZ_1M + SZ_512K),
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.inactive_period = DRM_MSM_INACTIVE_PERIOD,
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.init = a4xx_gpu_init,
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}, {
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.rev = ADRENO_REV(5, 3, 0, 2),
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.revn = 530,
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.name = "A530",
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.fw = {
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[ADRENO_FW_PM4] = "a530_pm4.fw",
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[ADRENO_FW_PFP] = "a530_pfp.fw",
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[ADRENO_FW_GPMU] = "a530v3_gpmu.fw2",
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},
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.gmem = SZ_1M,
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/*
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* Increase inactive period to 250 to avoid bouncing
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* the GDSC which appears to make it grumpy
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*/
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.inactive_period = 250,
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.quirks = ADRENO_QUIRK_TWO_PASS_USE_WFI |
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ADRENO_QUIRK_FAULT_DETECT_MASK,
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.init = a5xx_gpu_init,
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.zapfw = "a530_zap.mdt",
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}, {
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.rev = ADRENO_REV(6, 3, 0, ANY_ID),
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.revn = 630,
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.name = "A630",
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.fw = {
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[ADRENO_FW_SQE] = "a630_sqe.fw",
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[ADRENO_FW_GMU] = "a630_gmu.bin",
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},
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.gmem = SZ_1M,
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.init = a6xx_gpu_init,
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},
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};
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MODULE_FIRMWARE("qcom/a300_pm4.fw");
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MODULE_FIRMWARE("qcom/a300_pfp.fw");
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MODULE_FIRMWARE("qcom/a330_pm4.fw");
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MODULE_FIRMWARE("qcom/a330_pfp.fw");
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MODULE_FIRMWARE("qcom/a420_pm4.fw");
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MODULE_FIRMWARE("qcom/a420_pfp.fw");
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MODULE_FIRMWARE("qcom/a530_pm4.fw");
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MODULE_FIRMWARE("qcom/a530_pfp.fw");
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MODULE_FIRMWARE("qcom/a530v3_gpmu.fw2");
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MODULE_FIRMWARE("qcom/a530_zap.mdt");
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MODULE_FIRMWARE("qcom/a530_zap.b00");
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MODULE_FIRMWARE("qcom/a530_zap.b01");
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MODULE_FIRMWARE("qcom/a530_zap.b02");
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MODULE_FIRMWARE("qcom/a630_sqe.fw");
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MODULE_FIRMWARE("qcom/a630_gmu.bin");
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static inline bool _rev_match(uint8_t entry, uint8_t id)
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{
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return (entry == ANY_ID) || (entry == id);
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}
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const struct adreno_info *adreno_info(struct adreno_rev rev)
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{
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int i;
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/* identify gpu: */
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for (i = 0; i < ARRAY_SIZE(gpulist); i++) {
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const struct adreno_info *info = &gpulist[i];
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if (_rev_match(info->rev.core, rev.core) &&
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_rev_match(info->rev.major, rev.major) &&
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_rev_match(info->rev.minor, rev.minor) &&
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_rev_match(info->rev.patchid, rev.patchid))
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return info;
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}
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return NULL;
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}
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struct msm_gpu *adreno_load_gpu(struct drm_device *dev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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struct platform_device *pdev = priv->gpu_pdev;
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struct msm_gpu *gpu = NULL;
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struct adreno_gpu *adreno_gpu;
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int ret;
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if (pdev)
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gpu = platform_get_drvdata(pdev);
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if (!gpu) {
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dev_err_once(dev->dev, "no GPU device was found\n");
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return NULL;
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}
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adreno_gpu = to_adreno_gpu(gpu);
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/*
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* The number one reason for HW init to fail is if the firmware isn't
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* loaded yet. Try that first and don't bother continuing on
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* otherwise
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*/
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ret = adreno_load_fw(adreno_gpu);
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if (ret)
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return NULL;
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/* Make sure pm runtime is active and reset any previous errors */
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pm_runtime_set_active(&pdev->dev);
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ret = pm_runtime_get_sync(&pdev->dev);
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if (ret < 0) {
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dev_err(dev->dev, "Couldn't power up the GPU: %d\n", ret);
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return NULL;
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}
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mutex_lock(&dev->struct_mutex);
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ret = msm_gpu_hw_init(gpu);
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mutex_unlock(&dev->struct_mutex);
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pm_runtime_put_autosuspend(&pdev->dev);
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if (ret) {
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dev_err(dev->dev, "gpu hw init failed: %d\n", ret);
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return NULL;
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}
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#ifdef CONFIG_DEBUG_FS
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if (gpu->funcs->debugfs_init) {
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gpu->funcs->debugfs_init(gpu, dev->primary);
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gpu->funcs->debugfs_init(gpu, dev->render);
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}
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#endif
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return gpu;
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}
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static void set_gpu_pdev(struct drm_device *dev,
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struct platform_device *pdev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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priv->gpu_pdev = pdev;
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}
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static int find_chipid(struct device *dev, struct adreno_rev *rev)
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{
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struct device_node *node = dev->of_node;
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const char *compat;
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int ret;
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u32 chipid;
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/* first search the compat strings for qcom,adreno-XYZ.W: */
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ret = of_property_read_string_index(node, "compatible", 0, &compat);
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if (ret == 0) {
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unsigned int r, patch;
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if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2) {
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rev->core = r / 100;
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r %= 100;
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rev->major = r / 10;
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r %= 10;
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rev->minor = r;
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rev->patchid = patch;
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return 0;
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}
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}
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/* and if that fails, fall back to legacy "qcom,chipid" property: */
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ret = of_property_read_u32(node, "qcom,chipid", &chipid);
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if (ret) {
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dev_err(dev, "could not parse qcom,chipid: %d\n", ret);
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return ret;
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}
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rev->core = (chipid >> 24) & 0xff;
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rev->major = (chipid >> 16) & 0xff;
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rev->minor = (chipid >> 8) & 0xff;
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rev->patchid = (chipid & 0xff);
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dev_warn(dev, "Using legacy qcom,chipid binding!\n");
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dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n",
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rev->core, rev->major, rev->minor, rev->patchid);
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return 0;
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}
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static int adreno_bind(struct device *dev, struct device *master, void *data)
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{
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static struct adreno_platform_config config = {};
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const struct adreno_info *info;
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struct drm_device *drm = dev_get_drvdata(master);
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struct msm_gpu *gpu;
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int ret;
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ret = find_chipid(dev, &config.rev);
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if (ret)
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return ret;
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dev->platform_data = &config;
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set_gpu_pdev(drm, to_platform_device(dev));
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info = adreno_info(config.rev);
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if (!info) {
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dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n",
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config.rev.core, config.rev.major,
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config.rev.minor, config.rev.patchid);
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return -ENXIO;
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}
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DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major,
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config.rev.minor, config.rev.patchid);
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gpu = info->init(drm);
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if (IS_ERR(gpu)) {
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dev_warn(drm->dev, "failed to load adreno gpu\n");
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return PTR_ERR(gpu);
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}
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dev_set_drvdata(dev, gpu);
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return 0;
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}
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static void adreno_unbind(struct device *dev, struct device *master,
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void *data)
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{
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struct msm_gpu *gpu = dev_get_drvdata(dev);
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gpu->funcs->pm_suspend(gpu);
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gpu->funcs->destroy(gpu);
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set_gpu_pdev(dev_get_drvdata(master), NULL);
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}
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static const struct component_ops a3xx_ops = {
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.bind = adreno_bind,
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.unbind = adreno_unbind,
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};
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static int adreno_probe(struct platform_device *pdev)
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{
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return component_add(&pdev->dev, &a3xx_ops);
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}
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static int adreno_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &a3xx_ops);
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return 0;
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}
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static const struct of_device_id dt_match[] = {
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{ .compatible = "qcom,adreno" },
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{ .compatible = "qcom,adreno-3xx" },
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/* for backwards compat w/ downstream kgsl DT files: */
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{ .compatible = "qcom,kgsl-3d0" },
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{}
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};
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#ifdef CONFIG_PM
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static int adreno_resume(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct msm_gpu *gpu = platform_get_drvdata(pdev);
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return gpu->funcs->pm_resume(gpu);
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}
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static int adreno_suspend(struct device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev);
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struct msm_gpu *gpu = platform_get_drvdata(pdev);
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return gpu->funcs->pm_suspend(gpu);
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}
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#endif
|
||
|
|
|
||
|
|
static const struct dev_pm_ops adreno_pm_ops = {
|
||
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
|
||
|
|
SET_RUNTIME_PM_OPS(adreno_suspend, adreno_resume, NULL)
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_driver adreno_driver = {
|
||
|
|
.probe = adreno_probe,
|
||
|
|
.remove = adreno_remove,
|
||
|
|
.driver = {
|
||
|
|
.name = "adreno",
|
||
|
|
.of_match_table = dt_match,
|
||
|
|
.pm = &adreno_pm_ops,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
void __init adreno_register(void)
|
||
|
|
{
|
||
|
|
platform_driver_register(&adreno_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
void __exit adreno_unregister(void)
|
||
|
|
{
|
||
|
|
platform_driver_unregister(&adreno_driver);
|
||
|
|
}
|