434 lines
11 KiB
C
434 lines
11 KiB
C
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/* $Id: bkm_a8.c,v 1.22.2.4 2004/01/15 14:02:34 keil Exp $
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*
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* low level stuff for Scitel Quadro (4*S0, passive)
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*
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* Author Roland Klabunde
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* Copyright by Roland Klabunde <R.Klabunde@Berkom.de>
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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*/
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#include <linux/init.h>
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#include "hisax.h"
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#include "isac.h"
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#include "ipac.h"
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#include "hscx.h"
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#include "isdnl1.h"
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#include <linux/pci.h>
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#include "bkm_ax.h"
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#define ATTEMPT_PCI_REMAPPING /* Required for PLX rev 1 */
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static const char sct_quadro_revision[] = "$Revision: 1.22.2.4 $";
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static const char *sct_quadro_subtypes[] =
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{
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"",
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"#1",
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"#2",
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"#3",
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"#4"
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};
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#define wordout(addr, val) outw(val, addr)
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#define wordin(addr) inw(addr)
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static inline u_char
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readreg(unsigned int ale, unsigned int adr, u_char off)
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{
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register u_char ret;
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wordout(ale, off);
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ret = wordin(adr) & 0xFF;
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return (ret);
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}
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static inline void
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readfifo(unsigned int ale, unsigned int adr, u_char off, u_char *data, int size)
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{
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int i;
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wordout(ale, off);
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for (i = 0; i < size; i++)
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data[i] = wordin(adr) & 0xFF;
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}
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static inline void
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writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)
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{
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wordout(ale, off);
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wordout(adr, data);
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}
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static inline void
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writefifo(unsigned int ale, unsigned int adr, u_char off, u_char *data, int size)
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{
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int i;
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wordout(ale, off);
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for (i = 0; i < size; i++)
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wordout(adr, data[i]);
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}
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/* Interface functions */
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static u_char
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ReadISAC(struct IsdnCardState *cs, u_char offset)
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{
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return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80));
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}
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static void
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WriteISAC(struct IsdnCardState *cs, u_char offset, u_char value)
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{
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writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value);
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}
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static void
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ReadISACfifo(struct IsdnCardState *cs, u_char *data, int size)
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{
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readfifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
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}
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static void
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WriteISACfifo(struct IsdnCardState *cs, u_char *data, int size)
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{
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writefifo(cs->hw.ax.base, cs->hw.ax.data_adr, 0x80, data, size);
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}
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static u_char
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ReadHSCX(struct IsdnCardState *cs, int hscx, u_char offset)
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{
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return (readreg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0)));
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}
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static void
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WriteHSCX(struct IsdnCardState *cs, int hscx, u_char offset, u_char value)
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{
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writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value);
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}
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/* Set the specific ipac to active */
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static void
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set_ipac_active(struct IsdnCardState *cs, u_int active)
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{
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/* set irq mask */
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writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK,
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active ? 0xc0 : 0xff);
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}
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/*
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* fast interrupt HSCX stuff goes here
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*/
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#define READHSCX(cs, nr, reg) readreg(cs->hw.ax.base, \
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cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0))
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#define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \
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cs->hw.ax.data_adr, reg + (nr ? 0x40 : 0), data)
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#define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.ax.base, \
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cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
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#define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.ax.base, \
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cs->hw.ax.data_adr, (nr ? 0x40 : 0), ptr, cnt)
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#include "hscx_irq.c"
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static irqreturn_t
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bkm_interrupt_ipac(int intno, void *dev_id)
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{
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struct IsdnCardState *cs = dev_id;
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u_char ista, val, icnt = 5;
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u_long flags;
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spin_lock_irqsave(&cs->lock, flags);
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ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
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if (!(ista & 0x3f)) { /* not this IPAC */
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spin_unlock_irqrestore(&cs->lock, flags);
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return IRQ_NONE;
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}
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Start_IPAC:
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if (cs->debug & L1_DEB_IPAC)
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debugl1(cs, "IPAC ISTA %02X", ista);
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if (ista & 0x0f) {
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val = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, HSCX_ISTA + 0x40);
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if (ista & 0x01)
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val |= 0x01;
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if (ista & 0x04)
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val |= 0x02;
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if (ista & 0x08)
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val |= 0x04;
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if (val) {
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hscx_int_main(cs, val);
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}
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}
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if (ista & 0x20) {
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val = 0xfe & readreg(cs->hw.ax.base, cs->hw.ax.data_adr, ISAC_ISTA | 0x80);
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if (val) {
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isac_interrupt(cs, val);
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}
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}
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if (ista & 0x10) {
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val = 0x01;
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isac_interrupt(cs, val);
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}
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ista = readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ISTA);
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if ((ista & 0x3f) && icnt) {
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icnt--;
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goto Start_IPAC;
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}
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if (!icnt)
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printk(KERN_WARNING "HiSax: Scitel Quadro (%s) IRQ LOOP\n",
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sct_quadro_subtypes[cs->subtyp]);
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writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF);
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writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0);
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spin_unlock_irqrestore(&cs->lock, flags);
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return IRQ_HANDLED;
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}
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static void
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release_io_sct_quadro(struct IsdnCardState *cs)
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{
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release_region(cs->hw.ax.base & 0xffffffc0, 128);
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if (cs->subtyp == SCT_1)
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release_region(cs->hw.ax.plx_adr, 64);
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}
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static void
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enable_bkm_int(struct IsdnCardState *cs, unsigned bEnable)
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{
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if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
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if (bEnable)
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wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) | 0x41));
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else
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wordout(cs->hw.ax.plx_adr + 0x4C, (wordin(cs->hw.ax.plx_adr + 0x4C) & ~0x41));
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}
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}
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static void
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reset_bkm(struct IsdnCardState *cs)
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{
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if (cs->subtyp == SCT_1) {
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wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) & ~4));
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mdelay(10);
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/* Remove the soft reset */
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wordout(cs->hw.ax.plx_adr + 0x50, (wordin(cs->hw.ax.plx_adr + 0x50) | 4));
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mdelay(10);
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}
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}
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static int
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BKM_card_msg(struct IsdnCardState *cs, int mt, void *arg)
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{
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u_long flags;
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switch (mt) {
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case CARD_RESET:
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spin_lock_irqsave(&cs->lock, flags);
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/* Disable ints */
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set_ipac_active(cs, 0);
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enable_bkm_int(cs, 0);
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reset_bkm(cs);
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spin_unlock_irqrestore(&cs->lock, flags);
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return (0);
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case CARD_RELEASE:
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/* Sanity */
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spin_lock_irqsave(&cs->lock, flags);
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set_ipac_active(cs, 0);
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enable_bkm_int(cs, 0);
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spin_unlock_irqrestore(&cs->lock, flags);
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release_io_sct_quadro(cs);
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return (0);
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case CARD_INIT:
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spin_lock_irqsave(&cs->lock, flags);
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cs->debug |= L1_DEB_IPAC;
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set_ipac_active(cs, 1);
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inithscxisac(cs, 3);
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/* Enable ints */
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enable_bkm_int(cs, 1);
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spin_unlock_irqrestore(&cs->lock, flags);
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return (0);
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case CARD_TEST:
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return (0);
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}
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return (0);
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}
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static int sct_alloc_io(u_int adr, u_int len)
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{
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if (!request_region(adr, len, "scitel")) {
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printk(KERN_WARNING
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"HiSax: Scitel port %#x-%#x already in use\n",
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adr, adr + len);
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return (1);
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}
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return (0);
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}
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static struct pci_dev *dev_a8 = NULL;
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static u16 sub_vendor_id = 0;
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static u16 sub_sys_id = 0;
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static u_char pci_bus = 0;
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static u_char pci_device_fn = 0;
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static u_char pci_irq = 0;
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int setup_sct_quadro(struct IsdnCard *card)
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{
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struct IsdnCardState *cs = card->cs;
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char tmp[64];
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u_int found = 0;
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u_int pci_ioaddr1, pci_ioaddr2, pci_ioaddr3, pci_ioaddr4, pci_ioaddr5;
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strcpy(tmp, sct_quadro_revision);
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printk(KERN_INFO "HiSax: T-Berkom driver Rev. %s\n", HiSax_getrev(tmp));
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if (cs->typ == ISDN_CTYPE_SCT_QUADRO) {
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cs->subtyp = SCT_1; /* Preset */
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} else
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return (0);
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/* Identify subtype by para[0] */
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if (card->para[0] >= SCT_1 && card->para[0] <= SCT_4)
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cs->subtyp = card->para[0];
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else {
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printk(KERN_WARNING "HiSax: Scitel Quadro: Invalid "
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"subcontroller in configuration, default to 1\n");
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return (0);
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}
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if ((cs->subtyp != SCT_1) && ((sub_sys_id != PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) ||
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(sub_vendor_id != PCI_VENDOR_ID_BERKOM)))
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return (0);
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if (cs->subtyp == SCT_1) {
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while ((dev_a8 = hisax_find_pci_device(PCI_VENDOR_ID_PLX,
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PCI_DEVICE_ID_PLX_9050, dev_a8))) {
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sub_vendor_id = dev_a8->subsystem_vendor;
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sub_sys_id = dev_a8->subsystem_device;
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if ((sub_sys_id == PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO) &&
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(sub_vendor_id == PCI_VENDOR_ID_BERKOM)) {
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if (pci_enable_device(dev_a8))
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return (0);
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pci_ioaddr1 = pci_resource_start(dev_a8, 1);
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pci_irq = dev_a8->irq;
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pci_bus = dev_a8->bus->number;
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pci_device_fn = dev_a8->devfn;
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found = 1;
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break;
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}
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}
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if (!found) {
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printk(KERN_WARNING "HiSax: Scitel Quadro (%s): "
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"Card not found\n",
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sct_quadro_subtypes[cs->subtyp]);
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return (0);
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}
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#ifdef ATTEMPT_PCI_REMAPPING
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/* HACK: PLX revision 1 bug: PLX address bit 7 must not be set */
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if ((pci_ioaddr1 & 0x80) && (dev_a8->revision == 1)) {
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printk(KERN_WARNING "HiSax: Scitel Quadro (%s): "
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"PLX rev 1, remapping required!\n",
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sct_quadro_subtypes[cs->subtyp]);
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/* Restart PCI negotiation */
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pci_write_config_dword(dev_a8, PCI_BASE_ADDRESS_1, (u_int)-1);
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/* Move up by 0x80 byte */
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pci_ioaddr1 += 0x80;
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pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
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pci_write_config_dword(dev_a8, PCI_BASE_ADDRESS_1, pci_ioaddr1);
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dev_a8->resource[1].start = pci_ioaddr1;
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}
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#endif /* End HACK */
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}
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if (!pci_irq) { /* IRQ range check ?? */
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printk(KERN_WARNING "HiSax: Scitel Quadro (%s): No IRQ\n",
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sct_quadro_subtypes[cs->subtyp]);
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return (0);
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}
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pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_1, &pci_ioaddr1);
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pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_2, &pci_ioaddr2);
|
||
|
|
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_3, &pci_ioaddr3);
|
||
|
|
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_4, &pci_ioaddr4);
|
||
|
|
pci_read_config_dword(dev_a8, PCI_BASE_ADDRESS_5, &pci_ioaddr5);
|
||
|
|
if (!pci_ioaddr1 || !pci_ioaddr2 || !pci_ioaddr3 || !pci_ioaddr4 || !pci_ioaddr5) {
|
||
|
|
printk(KERN_WARNING "HiSax: Scitel Quadro (%s): "
|
||
|
|
"No IO base address(es)\n",
|
||
|
|
sct_quadro_subtypes[cs->subtyp]);
|
||
|
|
return (0);
|
||
|
|
}
|
||
|
|
pci_ioaddr1 &= PCI_BASE_ADDRESS_IO_MASK;
|
||
|
|
pci_ioaddr2 &= PCI_BASE_ADDRESS_IO_MASK;
|
||
|
|
pci_ioaddr3 &= PCI_BASE_ADDRESS_IO_MASK;
|
||
|
|
pci_ioaddr4 &= PCI_BASE_ADDRESS_IO_MASK;
|
||
|
|
pci_ioaddr5 &= PCI_BASE_ADDRESS_IO_MASK;
|
||
|
|
/* Take over */
|
||
|
|
cs->irq = pci_irq;
|
||
|
|
cs->irq_flags |= IRQF_SHARED;
|
||
|
|
/* pci_ioaddr1 is unique to all subdevices */
|
||
|
|
/* pci_ioaddr2 is for the fourth subdevice only */
|
||
|
|
/* pci_ioaddr3 is for the third subdevice only */
|
||
|
|
/* pci_ioaddr4 is for the second subdevice only */
|
||
|
|
/* pci_ioaddr5 is for the first subdevice only */
|
||
|
|
cs->hw.ax.plx_adr = pci_ioaddr1;
|
||
|
|
/* Enter all ipac_base addresses */
|
||
|
|
switch (cs->subtyp) {
|
||
|
|
case 1:
|
||
|
|
cs->hw.ax.base = pci_ioaddr5 + 0x00;
|
||
|
|
if (sct_alloc_io(pci_ioaddr1, 128))
|
||
|
|
return (0);
|
||
|
|
if (sct_alloc_io(pci_ioaddr5, 64))
|
||
|
|
return (0);
|
||
|
|
/* disable all IPAC */
|
||
|
|
writereg(pci_ioaddr5, pci_ioaddr5 + 4,
|
||
|
|
IPAC_MASK, 0xFF);
|
||
|
|
writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c,
|
||
|
|
IPAC_MASK, 0xFF);
|
||
|
|
writereg(pci_ioaddr3 + 0x10, pci_ioaddr3 + 0x14,
|
||
|
|
IPAC_MASK, 0xFF);
|
||
|
|
writereg(pci_ioaddr2 + 0x20, pci_ioaddr2 + 0x24,
|
||
|
|
IPAC_MASK, 0xFF);
|
||
|
|
break;
|
||
|
|
case 2:
|
||
|
|
cs->hw.ax.base = pci_ioaddr4 + 0x08;
|
||
|
|
if (sct_alloc_io(pci_ioaddr4, 64))
|
||
|
|
return (0);
|
||
|
|
break;
|
||
|
|
case 3:
|
||
|
|
cs->hw.ax.base = pci_ioaddr3 + 0x10;
|
||
|
|
if (sct_alloc_io(pci_ioaddr3, 64))
|
||
|
|
return (0);
|
||
|
|
break;
|
||
|
|
case 4:
|
||
|
|
cs->hw.ax.base = pci_ioaddr2 + 0x20;
|
||
|
|
if (sct_alloc_io(pci_ioaddr2, 64))
|
||
|
|
return (0);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
/* For isac and hscx data path */
|
||
|
|
cs->hw.ax.data_adr = cs->hw.ax.base + 4;
|
||
|
|
|
||
|
|
printk(KERN_INFO "HiSax: Scitel Quadro (%s) configured at "
|
||
|
|
"0x%.4lX, 0x%.4lX, 0x%.4lX and IRQ %d\n",
|
||
|
|
sct_quadro_subtypes[cs->subtyp],
|
||
|
|
cs->hw.ax.plx_adr,
|
||
|
|
cs->hw.ax.base,
|
||
|
|
cs->hw.ax.data_adr,
|
||
|
|
cs->irq);
|
||
|
|
|
||
|
|
test_and_set_bit(HW_IPAC, &cs->HW_Flags);
|
||
|
|
|
||
|
|
cs->readisac = &ReadISAC;
|
||
|
|
cs->writeisac = &WriteISAC;
|
||
|
|
cs->readisacfifo = &ReadISACfifo;
|
||
|
|
cs->writeisacfifo = &WriteISACfifo;
|
||
|
|
|
||
|
|
cs->BC_Read_Reg = &ReadHSCX;
|
||
|
|
cs->BC_Write_Reg = &WriteHSCX;
|
||
|
|
cs->BC_Send_Data = &hscx_fill_fifo;
|
||
|
|
cs->cardmsg = &BKM_card_msg;
|
||
|
|
cs->irq_func = &bkm_interrupt_ipac;
|
||
|
|
|
||
|
|
printk(KERN_INFO "HiSax: Scitel Quadro (%s): IPAC Version %d\n",
|
||
|
|
sct_quadro_subtypes[cs->subtyp],
|
||
|
|
readreg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_ID));
|
||
|
|
return (1);
|
||
|
|
}
|