548 lines
15 KiB
C
548 lines
15 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 MediaTek Inc.
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* Author: Yu-Chang Wang <Yu-Chang.Wang@mediatek.com>
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*/
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#include <linux/device.h>
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#include <linux/module.h>
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#include "clk-fhctl-pll.h"
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#include "clk-fhctl-util.h"
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#define REG_ADDR(base, x) (void __iomem *)((unsigned long)base + (x))
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struct match {
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char *compatible;
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struct fh_pll_domain **domain_list;
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};
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static int init_v1(struct fh_pll_domain *d,
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void __iomem *fhctl_base,
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void __iomem *apmixed_base)
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{
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struct fh_pll_data *data;
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struct fh_pll_offset *offset;
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struct fh_pll_regs *regs;
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char *name;
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name = d->name;
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data = d->data;
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offset = d->offset;
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regs = d->regs;
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if (regs->reg_hp_en) {
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FHDBG("domain<%s> inited\n", name);
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return 0;
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}
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FHDBG("init domain<%s>\n", name);
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while (data->dds_mask != 0) {
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int regs_offset;
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/* fhctl common part */
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regs->reg_hp_en = REG_ADDR(fhctl_base,
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offset->offset_hp_en);
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regs->reg_clk_con = REG_ADDR(fhctl_base,
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offset->offset_clk_con);
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regs->reg_rst_con = REG_ADDR(fhctl_base,
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offset->offset_rst_con);
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regs->reg_slope0 = REG_ADDR(fhctl_base,
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offset->offset_slope0);
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regs->reg_slope1 = REG_ADDR(fhctl_base,
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offset->offset_slope1);
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/* fhctl pll part */
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regs_offset = offset->offset_fhctl + offset->offset_cfg;
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regs->reg_cfg = REG_ADDR(fhctl_base, regs_offset);
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regs->reg_updnlmt = REG_ADDR(regs->reg_cfg,
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offset->offset_updnlmt);
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regs->reg_dds = REG_ADDR(regs->reg_cfg,
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offset->offset_dds);
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regs->reg_dvfs = REG_ADDR(regs->reg_cfg,
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offset->offset_dvfs);
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regs->reg_mon = REG_ADDR(regs->reg_cfg,
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offset->offset_mon);
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/* apmixed part */
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regs->reg_con_pcw = REG_ADDR(apmixed_base,
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offset->offset_con_pcw);
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FHDBG("pll<%s>, dds_mask<%d>, data<%x> offset<%x> regs<%x>\n",
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data->name, data->dds_mask, data, offset, regs);
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data++;
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offset++;
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regs++;
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}
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return 0;
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}
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/* platform data begin */
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/* 6853 begin */
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#define SIZE_6853_TOP (sizeof(mt6853_top_data)\
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/sizeof(struct fh_pll_data))
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#define DATA_6853_TOP(_name) { \
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.name = _name, \
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.dds_mask = GENMASK(21, 0), \
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.slope0_value = 0x6003c97, \
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.slope1_value = 0x6003c97, \
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.sfstrx_en = BIT(2), \
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.frddsx_en = BIT(1), \
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.fhctlx_en = BIT(0), \
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.tgl_org = BIT(31), \
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.dvfs_tri = BIT(31), \
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.pcwchg = BIT(31), \
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.dt_val = 0x0, \
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.df_val = 0x9, \
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.updnlmt_shft = 16, \
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.msk_frddsx_dys = GENMASK(23, 20), \
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.msk_frddsx_dts = GENMASK(19, 16), \
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}
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#define OFFSET_6853_TOP(_fhctl, _con_pcw) { \
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.offset_fhctl = _fhctl, \
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.offset_con_pcw = _con_pcw, \
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.offset_hp_en = 0x0, \
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.offset_clk_con = 0x8, \
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.offset_rst_con = 0xc, \
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.offset_slope0 = 0x10, \
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.offset_slope1 = 0x14, \
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.offset_cfg = 0x0, \
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.offset_updnlmt = 0x4, \
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.offset_dds = 0x8, \
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.offset_dvfs = 0xc, \
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.offset_mon = 0x10, \
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}
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static struct fh_pll_data mt6853_top_data[] = {
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DATA_6853_TOP("armpll_ll"),
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DATA_6853_TOP("armpll_bl0"),
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DATA_6853_TOP("armpll_bl1"),
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DATA_6853_TOP("armpll_bl2"),
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DATA_6853_TOP("npupll"),
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DATA_6853_TOP("ccipll"),
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DATA_6853_TOP("mfgpll"),
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DATA_6853_TOP("mempll"),
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DATA_6853_TOP("mpll"),
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DATA_6853_TOP("mmpll"),
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DATA_6853_TOP("mainpll"),
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DATA_6853_TOP("msdcpll"),
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DATA_6853_TOP("adsppll"),
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DATA_6853_TOP("apupll"),
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DATA_6853_TOP("tvdpll"),
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{}
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};
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static struct fh_pll_offset mt6853_top_offset[SIZE_6853_TOP] = {
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OFFSET_6853_TOP(0x003C, 0x020C),
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OFFSET_6853_TOP(0x0050, 0x021C),
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OFFSET_6853_TOP(0x0064, 0x022C),
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OFFSET_6853_TOP(0x0078, 0x023C),
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OFFSET_6853_TOP(0x008C, 0x03B8),
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OFFSET_6853_TOP(0x00A0, 0x025C),
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OFFSET_6853_TOP(0x00B4, 0x026C),
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OFFSET_6853_TOP(0x00C8, 0xffff),
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OFFSET_6853_TOP(0x00DC, 0x0394),
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OFFSET_6853_TOP(0x00F0, 0x0364),
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OFFSET_6853_TOP(0x0104, 0x0344),
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OFFSET_6853_TOP(0x0118, 0x0354),
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OFFSET_6853_TOP(0x012c, 0x0374),
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OFFSET_6853_TOP(0x0140, 0xffff),
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OFFSET_6853_TOP(0x0154, 0x0384),
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{}
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};
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static struct fh_pll_regs mt6853_top_regs[SIZE_6853_TOP];
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static struct fh_pll_domain mt6853_top = {
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.name = "top",
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.data = (struct fh_pll_data *)&mt6853_top_data,
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.offset = (struct fh_pll_offset *)&mt6853_top_offset,
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.regs = (struct fh_pll_regs *)&mt6853_top_regs,
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.init = &init_v1,
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};
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static struct fh_pll_domain *mt6853_domain[] = {
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&mt6853_top,
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NULL
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};
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static struct match mt6853_match = {
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.compatible = "mediatek,mt6853-fhctl",
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.domain_list = (struct fh_pll_domain **)mt6853_domain,
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};
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/* 6853 end */
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/* 6877 begin */
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#define SIZE_6877_TOP (sizeof(mt6877_top_data)\
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/sizeof(struct fh_pll_data))
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#define DATA_6877_TOP(_name) { \
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.name = _name, \
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.dds_mask = GENMASK(21, 0), \
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.slope0_value = 0x6003c97, \
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.slope1_value = 0x6003c97, \
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.sfstrx_en = BIT(2), \
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.frddsx_en = BIT(1), \
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.fhctlx_en = BIT(0), \
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.tgl_org = BIT(31), \
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.dvfs_tri = BIT(31), \
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.pcwchg = BIT(31), \
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.dt_val = 0x0, \
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.df_val = 0x9, \
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.updnlmt_shft = 16, \
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.msk_frddsx_dys = GENMASK(23, 20), \
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.msk_frddsx_dts = GENMASK(19, 16), \
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}
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#define OFFSET_6877_TOP(_fhctl, _con_pcw) { \
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.offset_fhctl = _fhctl, \
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.offset_con_pcw = _con_pcw, \
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.offset_hp_en = 0x0, \
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.offset_clk_con = 0x8, \
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.offset_rst_con = 0xc, \
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.offset_slope0 = 0x10, \
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.offset_slope1 = 0x14, \
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.offset_cfg = 0x0, \
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.offset_updnlmt = 0x4, \
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.offset_dds = 0x8, \
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.offset_dvfs = 0xc, \
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.offset_mon = 0x10, \
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}
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static struct fh_pll_data mt6877_top_data[] = {
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DATA_6877_TOP("armpll_ll"),
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DATA_6877_TOP("armpll_bl0"),
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DATA_6877_TOP("armpll_b"),
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DATA_6877_TOP("ccipll"),
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DATA_6877_TOP("mempll"),
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DATA_6877_TOP("emipll"),
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DATA_6877_TOP("mpll"),
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DATA_6877_TOP("mmpll"),
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DATA_6877_TOP("mainpll"),
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DATA_6877_TOP("msdcpll"),
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DATA_6877_TOP("adsppll"),
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DATA_6877_TOP("imgpll"),
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DATA_6877_TOP("tvdpll"),
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{}
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};
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static struct fh_pll_offset mt6877_top_offset[] = {
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OFFSET_6877_TOP(0x003C, 0x020C), // FHCTL0_CFG, ARMPLL_LL_CON1
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OFFSET_6877_TOP(0x0050, 0x021C), // FHCTL1_CFG, ARMPLL_BL_CON1
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OFFSET_6877_TOP(0x0064, 0x022C), // FHCTL2_CFG, ARMPLL_B_CON1
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OFFSET_6877_TOP(0x0078, 0x023C), // FHCTL3_CFG, CCIPLL_CON1
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OFFSET_6877_TOP(0x008C, 0xffff), // FHCTL4_CFG,
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OFFSET_6877_TOP(0x00A0, 0x03B4), // FHCTL5_CFG, EMIPLL_CON1
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OFFSET_6877_TOP(0x00B4, 0x0394), // FHCTL6_CFG, MPLL_CON1
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OFFSET_6877_TOP(0x00C8, 0x03A4), // FHCTL7_CFG, MMPLL_CON1
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OFFSET_6877_TOP(0x00DC, 0x0354), // FHCTL8_CFG, MAINPLL_CON1
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OFFSET_6877_TOP(0x00F0, 0x0364), // FHCTL9_CFG, MSDCPLL_CON1
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OFFSET_6877_TOP(0x0104, 0x0384), // FHCTL10_CFG, ADSPPLL_CON1
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OFFSET_6877_TOP(0x0118, 0x0374), // FHCTL11_CFG, IMGPLL_CON1
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OFFSET_6877_TOP(0x012c, 0x024c), // FHCTL12_CFG, TVDPLL_CON1
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{}
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};
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#define SIZE_6877_GPU (sizeof(mt6877_gpu_data)\
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/sizeof(struct fh_pll_data))
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static struct fh_pll_data mt6877_gpu_data[] = {
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DATA_6877_TOP("mfgpll1"),
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DATA_6877_TOP("mfgpll2"),
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DATA_6877_TOP("mfgpll3"),
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DATA_6877_TOP("mfgpll4"),
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{}
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};
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static struct fh_pll_offset mt6877_gpu_offset[] = {
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OFFSET_6877_TOP(0x003C, 0x000C), // PLL4H_FHCTL0_CFG, PLL4H_PLL1_CON1
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OFFSET_6877_TOP(0x0050, 0x001C), // PLL4HPLL_FHCTL1_CFG, PLL4H_PLL2_CON1
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OFFSET_6877_TOP(0x0064, 0x002C), // PLL4HPLL_FHCTL2_CFG, PLL4H_PLL3_CON1
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OFFSET_6877_TOP(0x0078, 0x003C), // PLL4HPLL_FHCTL3_CFG, PLL4H_PLL4_CON1
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{}
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};
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#define SIZE_6877_APU (sizeof(mt6877_apu_data)\
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/sizeof(struct fh_pll_data))
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static struct fh_pll_data mt6877_apu_data[] = {
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DATA_6877_TOP("apupll"),
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DATA_6877_TOP("npupll"),
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DATA_6877_TOP("apupll1"),
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DATA_6877_TOP("apupll2"),
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{}
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};
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static struct fh_pll_offset mt6877_apu_offset[] = {
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OFFSET_6877_TOP(0x003C, 0x000C), // PLL4HPLL_FHCTL0_CFG, PLL4H_PLL1_CON1
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OFFSET_6877_TOP(0x0050, 0x001C), // PLL4HPLL_FHCTL1_CFG, PLL4H_PLL2_CON1
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OFFSET_6877_TOP(0x0064, 0x002C), // PLL4HPLL_FHCTL2_CFG, PLL4H_PLL3_CON1
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OFFSET_6877_TOP(0x0078, 0x003C), // PLL4HPLL_FHCTL3_CFG, PLL4H_PLL4_CON1
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{}
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};
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static struct fh_pll_regs mt6877_top_regs[SIZE_6877_TOP];
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static struct fh_pll_regs mt6877_gpu_regs[SIZE_6877_GPU];
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static struct fh_pll_regs mt6877_apu_regs[SIZE_6877_APU];
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static struct fh_pll_domain mt6877_top = {
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.name = "top",
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.data = (struct fh_pll_data *)&mt6877_top_data,
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.offset = (struct fh_pll_offset *)&mt6877_top_offset,
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.regs = (struct fh_pll_regs *)&mt6877_top_regs,
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.init = &init_v1,
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};
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static struct fh_pll_domain mt6877_gpu = {
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.name = "gpu",
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.data = (struct fh_pll_data *)&mt6877_gpu_data,
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.offset = (struct fh_pll_offset *)&mt6877_gpu_offset,
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.regs = (struct fh_pll_regs *)&mt6877_gpu_regs,
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.init = &init_v1,
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};
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static struct fh_pll_domain mt6877_apu = {
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.name = "apu",
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.data = (struct fh_pll_data *)&mt6877_apu_data,
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.offset = (struct fh_pll_offset *)&mt6877_apu_offset,
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.regs = (struct fh_pll_regs *)&mt6877_apu_regs,
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.init = &init_v1,
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};
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static struct fh_pll_domain *mt6877_domain[] = {
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&mt6877_top,
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&mt6877_gpu,
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&mt6877_apu,
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NULL,
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};
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static struct match mt6877_match = {
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.compatible = "mediatek,mt6877-fhctl",
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.domain_list = (struct fh_pll_domain **)mt6877_domain,
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};
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/* 6877 end */
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/* platform data begin */
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/* 6873 begin */
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#define SIZE_6873_TOP (sizeof(mt6873_top_data)\
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/sizeof(struct fh_pll_data))
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#define DATA_6873_TOP(_name) { \
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.name = _name, \
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.dds_mask = GENMASK(21, 0), \
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.slope0_value = 0x6003c97, \
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.slope1_value = 0x6003c97, \
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.sfstrx_en = BIT(2), \
|
||
|
|
.frddsx_en = BIT(1), \
|
||
|
|
.fhctlx_en = BIT(0), \
|
||
|
|
.tgl_org = BIT(31), \
|
||
|
|
.dvfs_tri = BIT(31), \
|
||
|
|
.pcwchg = BIT(31), \
|
||
|
|
.dt_val = 0x0, \
|
||
|
|
.df_val = 0x9, \
|
||
|
|
.updnlmt_shft = 16, \
|
||
|
|
.msk_frddsx_dys = GENMASK(23, 20), \
|
||
|
|
.msk_frddsx_dts = GENMASK(19, 16), \
|
||
|
|
}
|
||
|
|
#define OFFSET_6873_TOP(_fhctl, _con_pcw) { \
|
||
|
|
.offset_fhctl = _fhctl, \
|
||
|
|
.offset_con_pcw = _con_pcw, \
|
||
|
|
.offset_hp_en = 0x0, \
|
||
|
|
.offset_clk_con = 0x8, \
|
||
|
|
.offset_rst_con = 0xc, \
|
||
|
|
.offset_slope0 = 0x10, \
|
||
|
|
.offset_slope1 = 0x14, \
|
||
|
|
.offset_cfg = 0x0, \
|
||
|
|
.offset_updnlmt = 0x4, \
|
||
|
|
.offset_dds = 0x8, \
|
||
|
|
.offset_dvfs = 0xc, \
|
||
|
|
.offset_mon = 0x10, \
|
||
|
|
}
|
||
|
|
static struct fh_pll_data mt6873_top_data[] = {
|
||
|
|
DATA_6873_TOP("armpll_ll"),
|
||
|
|
DATA_6873_TOP("armpll_bl0"),
|
||
|
|
DATA_6873_TOP("armpll_bl1"),
|
||
|
|
DATA_6873_TOP("armpll_bl2"),
|
||
|
|
DATA_6873_TOP("npupll"),
|
||
|
|
DATA_6873_TOP("ccipll"),
|
||
|
|
DATA_6873_TOP("mfgpll"),
|
||
|
|
DATA_6873_TOP("mempll"),
|
||
|
|
DATA_6873_TOP("mpll"),
|
||
|
|
DATA_6873_TOP("mmpll"),
|
||
|
|
DATA_6873_TOP("mainpll"),
|
||
|
|
DATA_6873_TOP("msdcpll"),
|
||
|
|
DATA_6873_TOP("adsppll"),
|
||
|
|
DATA_6873_TOP("apupll"),
|
||
|
|
DATA_6873_TOP("tvdpll"),
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
static struct fh_pll_offset mt6873_top_offset[SIZE_6873_TOP] = {
|
||
|
|
OFFSET_6873_TOP(0x003C, 0x020C),
|
||
|
|
OFFSET_6873_TOP(0x0050, 0x021C),
|
||
|
|
OFFSET_6873_TOP(0x0064, 0x022C),
|
||
|
|
OFFSET_6873_TOP(0x0078, 0x023C),
|
||
|
|
OFFSET_6873_TOP(0x008C, 0x03B8),
|
||
|
|
OFFSET_6873_TOP(0x00A0, 0x025C),
|
||
|
|
OFFSET_6873_TOP(0x00B4, 0x026C),
|
||
|
|
OFFSET_6873_TOP(0x00C8, 0xffff),
|
||
|
|
OFFSET_6873_TOP(0x00DC, 0x0394),
|
||
|
|
OFFSET_6873_TOP(0x00F0, 0x0364),
|
||
|
|
OFFSET_6873_TOP(0x0104, 0x0344),
|
||
|
|
OFFSET_6873_TOP(0x0118, 0x0354),
|
||
|
|
OFFSET_6873_TOP(0x012c, 0x0374),
|
||
|
|
OFFSET_6873_TOP(0x0140, 0x03A4),
|
||
|
|
OFFSET_6873_TOP(0x0154, 0x0384),
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
static struct fh_pll_regs mt6873_top_regs[SIZE_6873_TOP];
|
||
|
|
static struct fh_pll_domain mt6873_top = {
|
||
|
|
.name = "top",
|
||
|
|
.data = (struct fh_pll_data *)&mt6873_top_data,
|
||
|
|
.offset = (struct fh_pll_offset *)&mt6873_top_offset,
|
||
|
|
.regs = (struct fh_pll_regs *)&mt6873_top_regs,
|
||
|
|
.init = &init_v1,
|
||
|
|
};
|
||
|
|
static struct fh_pll_domain *mt6873_domain[] = {
|
||
|
|
&mt6873_top,
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
static struct match mt6873_match = {
|
||
|
|
.compatible = "mediatek,mt6873-fhctl",
|
||
|
|
.domain_list = (struct fh_pll_domain **)mt6873_domain,
|
||
|
|
};
|
||
|
|
/* 6873 end */
|
||
|
|
|
||
|
|
/* platform data begin */
|
||
|
|
/* 6885 begin */
|
||
|
|
#define SIZE_6885_TOP (sizeof(mt6885_top_data)\
|
||
|
|
/sizeof(struct fh_pll_data))
|
||
|
|
#define DATA_6885_TOP(_name) { \
|
||
|
|
.name = _name, \
|
||
|
|
.dds_mask = GENMASK(21, 0), \
|
||
|
|
.slope0_value = 0x6003c97, \
|
||
|
|
.slope1_value = 0x6003c97, \
|
||
|
|
.sfstrx_en = BIT(2), \
|
||
|
|
.frddsx_en = BIT(1), \
|
||
|
|
.fhctlx_en = BIT(0), \
|
||
|
|
.tgl_org = BIT(31), \
|
||
|
|
.dvfs_tri = BIT(31), \
|
||
|
|
.pcwchg = BIT(31), \
|
||
|
|
.dt_val = 0x0, \
|
||
|
|
.df_val = 0x9, \
|
||
|
|
.updnlmt_shft = 16, \
|
||
|
|
.msk_frddsx_dys = GENMASK(23, 20), \
|
||
|
|
.msk_frddsx_dts = GENMASK(19, 16), \
|
||
|
|
}
|
||
|
|
#define OFFSET_6885_TOP(_fhctl, _con_pcw) { \
|
||
|
|
.offset_fhctl = _fhctl, \
|
||
|
|
.offset_con_pcw = _con_pcw, \
|
||
|
|
.offset_hp_en = 0x0, \
|
||
|
|
.offset_clk_con = 0x8, \
|
||
|
|
.offset_rst_con = 0xc, \
|
||
|
|
.offset_slope0 = 0x10, \
|
||
|
|
.offset_slope1 = 0x14, \
|
||
|
|
.offset_cfg = 0x0, \
|
||
|
|
.offset_updnlmt = 0x4, \
|
||
|
|
.offset_dds = 0x8, \
|
||
|
|
.offset_dvfs = 0xc, \
|
||
|
|
.offset_mon = 0x10, \
|
||
|
|
}
|
||
|
|
static struct fh_pll_data mt6885_top_data[] = {
|
||
|
|
DATA_6885_TOP("armpll_ll"),
|
||
|
|
DATA_6885_TOP("armpll_bl0"),
|
||
|
|
DATA_6885_TOP("armpll_bl1"),
|
||
|
|
DATA_6885_TOP("armpll_bl2"),
|
||
|
|
DATA_6885_TOP("armpll_bl3"),
|
||
|
|
DATA_6885_TOP("ccipll"),
|
||
|
|
DATA_6885_TOP("mfgpll"),
|
||
|
|
DATA_6885_TOP("mempll"),
|
||
|
|
DATA_6885_TOP("mpll"),
|
||
|
|
DATA_6885_TOP("mmpll"),
|
||
|
|
DATA_6885_TOP("mainpll"),
|
||
|
|
DATA_6885_TOP("msdcpll"),
|
||
|
|
DATA_6885_TOP("adsppll"),
|
||
|
|
DATA_6885_TOP("apupll"),
|
||
|
|
DATA_6885_TOP("tvdpll"),
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
static struct fh_pll_offset mt6885_top_offset[SIZE_6885_TOP] = {
|
||
|
|
OFFSET_6885_TOP(0x003C, 0x020C),
|
||
|
|
OFFSET_6885_TOP(0x0050, 0x021C),
|
||
|
|
OFFSET_6885_TOP(0x0064, 0x022C),
|
||
|
|
OFFSET_6885_TOP(0x0078, 0x023C),
|
||
|
|
OFFSET_6885_TOP(0x008C, 0x024C),
|
||
|
|
OFFSET_6885_TOP(0x00A0, 0x025C),
|
||
|
|
OFFSET_6885_TOP(0x00B4, 0x026C),
|
||
|
|
OFFSET_6885_TOP(0x00C8, 0xffff),
|
||
|
|
OFFSET_6885_TOP(0x00DC, 0x0394),
|
||
|
|
OFFSET_6885_TOP(0x00F0, 0x0364),
|
||
|
|
OFFSET_6885_TOP(0x0104, 0x0344),
|
||
|
|
OFFSET_6885_TOP(0x0118, 0x0354),
|
||
|
|
OFFSET_6885_TOP(0x012c, 0x0374),
|
||
|
|
OFFSET_6885_TOP(0x0140, 0x03A4),
|
||
|
|
OFFSET_6885_TOP(0x0154, 0x0384),
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
static struct fh_pll_regs mt6885_top_regs[SIZE_6885_TOP];
|
||
|
|
static struct fh_pll_domain mt6885_top = {
|
||
|
|
.name = "top",
|
||
|
|
.data = (struct fh_pll_data *)&mt6885_top_data,
|
||
|
|
.offset = (struct fh_pll_offset *)&mt6885_top_offset,
|
||
|
|
.regs = (struct fh_pll_regs *)&mt6885_top_regs,
|
||
|
|
.init = &init_v1,
|
||
|
|
};
|
||
|
|
static struct fh_pll_domain *mt6885_domain[] = {
|
||
|
|
&mt6885_top,
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
static struct match mt6885_match = {
|
||
|
|
.compatible = "mediatek,mt6885-fhctl",
|
||
|
|
.domain_list = (struct fh_pll_domain **)mt6885_domain,
|
||
|
|
};
|
||
|
|
/* 6885 end */
|
||
|
|
|
||
|
|
static const struct match *matchs[] = {
|
||
|
|
&mt6853_match,
|
||
|
|
&mt6877_match,
|
||
|
|
&mt6873_match,
|
||
|
|
&mt6885_match,
|
||
|
|
NULL
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct fh_pll_domain **get_list(char *comp)
|
||
|
|
{
|
||
|
|
struct match **match;
|
||
|
|
static struct fh_pll_domain **list;
|
||
|
|
|
||
|
|
match = (struct match **)matchs;
|
||
|
|
|
||
|
|
/* name used only if !list */
|
||
|
|
if (!list) {
|
||
|
|
while (*matchs != NULL) {
|
||
|
|
if (strcmp(comp,
|
||
|
|
(*match)->compatible) == 0) {
|
||
|
|
list = (*match)->domain_list;
|
||
|
|
FHDBG("target<%s>\n", comp);
|
||
|
|
break;
|
||
|
|
}
|
||
|
|
match++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
return list;
|
||
|
|
}
|
||
|
|
void init_fh_domain(const char *domain,
|
||
|
|
char *comp,
|
||
|
|
void __iomem *fhctl_base,
|
||
|
|
void __iomem *apmixed_base)
|
||
|
|
{
|
||
|
|
struct fh_pll_domain **list;
|
||
|
|
|
||
|
|
list = get_list(comp);
|
||
|
|
|
||
|
|
while (*list != NULL) {
|
||
|
|
if (strcmp(domain,
|
||
|
|
(*list)->name) == 0) {
|
||
|
|
(*list)->init(*list,
|
||
|
|
fhctl_base,
|
||
|
|
apmixed_base);
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
list++;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
struct fh_pll_domain *get_fh_domain(const char *domain)
|
||
|
|
{
|
||
|
|
struct fh_pll_domain **list;
|
||
|
|
|
||
|
|
list = get_list(NULL);
|
||
|
|
|
||
|
|
/* find instance */
|
||
|
|
while (*list != NULL) {
|
||
|
|
if (strcmp(domain,
|
||
|
|
(*list)->name) == 0)
|
||
|
|
return *list;
|
||
|
|
list++;
|
||
|
|
}
|
||
|
|
return NULL;
|
||
|
|
}
|